add tx clockhack

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index f6d11f1146b1016fe916cb64a5fb5a1e9df6b6a7..2d9f9dccdc62ae27bd4593b979b2957587d32a60 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -232,6 +232,12 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
             typ = p['type']
             pname = p['name']
             n = name  
+            if typ == 'out' or typ == 'inout':
+                if not n.startswith('gpio'):  # XXX EURGH! horrible hack
+                    n_ = "{0}{1}".format(n, count)
+                else:
+                    n_ = n
+                ret.append(template.format("Bit#(1)", n_, ck, spc))
             if typ == 'in' or typ == 'inout':
                 #fname = self.pinname_in(pname)
                 n_ = "{0}{1}".format(n, count)