Refactor and fix LR/SC implementation (#217)

[riscv-isa-sim.git] / riscv / insns / lr_d.h

diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h
index 077590f65950bc886b4af3150ba09b9f9a620658..52090c31b87ccfbf1ef216e461a17d421059ee24 100644 (file)
--- a/riscv/insns/lr_d.h
+++ b/riscv/insns/lr_d.h
@@ -1,4 +1,4 @@
 require_extension('A');
 require_rv64;
-p->get_state()->load_reservation = RS1;
+MMU.acquire_load_reservation(RS1);
 WRITE_RD(MMU.load_int64(RS1));