Refactor and fix LR/SC implementation (#217)

[riscv-isa-sim.git] / riscv / insns / sc_d.h

diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index 01a45ce9094af383e151d039863e8de6df42d9e3..aeeabd350d36e0c98e2c76bf02dc8adc1f87905b 100644 (file)
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -1,9 +1,11 @@
 require_extension('A');
 require_rv64;
-if (RS1 == p->get_state()->load_reservation)
+if (MMU.check_load_reservation(RS1))
 {
   MMU.store_uint64(RS1, RS2);
   WRITE_RD(0);
 }
 else
   WRITE_RD(1);
+
+MMU.yield_load_reservation();