Refactor and fix LR/SC implementation (#217)

[riscv-isa-sim.git] / riscv / insns / sc_w.h

diff --git a/riscv/insns/sc_w.h b/riscv/insns/sc_w.h
index 68ec57717aa190ca52e170b4047df859ce69e20d..4b4be505840b0102fe1ffa9c8e9712b9b0658f1d 100644 (file)
--- a/riscv/insns/sc_w.h
+++ b/riscv/insns/sc_w.h
@@ -1,8 +1,10 @@
 require_extension('A');
-if (RS1 == p->get_state()->load_reservation)
+if (MMU.check_load_reservation(RS1))
 {
   MMU.store_uint32(RS1, RS2);
   WRITE_RD(0);
 }
 else
   WRITE_RD(1);
+
+MMU.yield_load_reservation();