Refactor and fix LR/SC implementation (#217)

[riscv-isa-sim.git] / riscv / mmu.cc

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 3a0bd39b89471470cef1155f201a646b673cbfab..021f587eaac5ac23c42ae0fa8b88c93c4ca27ec5 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -12,6 +12,7 @@ mmu_t::mmu_t(simif_t* sim, processor_t* proc)
   matched_trigger(NULL)
 {
   flush_tlb();
+  yield_load_reservation();
 }
 
 mmu_t::~mmu_t()