13 from testlib
import assertEqual
, assertNotEqual
, assertIn
, assertNotIn
14 from testlib
import assertGreater
, assertRegexpMatches
, assertLess
15 from testlib
import GdbTest
, GdbSingleHartTest
, TestFailed
, assertTrue
17 MSTATUS_UIE
= 0x00000001
18 MSTATUS_SIE
= 0x00000002
19 MSTATUS_HIE
= 0x00000004
20 MSTATUS_MIE
= 0x00000008
21 MSTATUS_UPIE
= 0x00000010
22 MSTATUS_SPIE
= 0x00000020
23 MSTATUS_HPIE
= 0x00000040
24 MSTATUS_MPIE
= 0x00000080
25 MSTATUS_SPP
= 0x00000100
26 MSTATUS_HPP
= 0x00000600
27 MSTATUS_MPP
= 0x00001800
28 MSTATUS_FS
= 0x00006000
29 MSTATUS_XS
= 0x00018000
30 MSTATUS_MPRV
= 0x00020000
31 MSTATUS_PUM
= 0x00040000
32 MSTATUS_MXR
= 0x00080000
33 MSTATUS_VM
= 0x1F000000
34 MSTATUS32_SD
= 0x80000000
35 MSTATUS64_SD
= 0x8000000000000000
37 # pylint: disable=abstract-method
39 def ihex_line(address
, record_type
, data
):
40 assert len(data
) < 128
41 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
43 check
+= address
% 256
49 line
+= "%02X" % value
50 line
+= "%02X\n" % ((256-check
)%256)
54 assert line
.startswith(":")
56 data_len
= int(line
[:2], 16)
57 address
= int(line
[2:6], 16)
58 record_type
= int(line
[6:8], 16)
60 for i
in range(data_len
):
61 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
62 return record_type
, address
, data
64 def readable_binary_string(s
):
65 return "".join("%02x" % ord(c
) for c
in s
)
67 class SimpleRegisterTest(GdbTest
):
68 def check_reg(self
, name
, alias
):
69 a
= random
.randrange(1<<self
.hart
.xlen
)
70 b
= random
.randrange(1<<self
.hart
.xlen
)
71 self
.gdb
.p("$%s=0x%x" % (name
, a
))
72 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
74 assertEqual(self
.gdb
.p("$%s" % name
), a
)
75 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
76 self
.gdb
.p("$%s=0x%x" % (alias
, b
))
77 assertEqual(self
.gdb
.p("$%s" % name
), b
)
79 assertEqual(self
.gdb
.p("$%s" % name
), b
)
80 assertEqual(self
.gdb
.p("$%s" % alias
), b
)
84 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
85 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
86 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
87 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 12))
88 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 16))
89 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
91 class SimpleS0Test(SimpleRegisterTest
):
93 self
.check_reg("s0", "x8")
95 class SimpleS1Test(SimpleRegisterTest
):
97 self
.check_reg("s1", "x9")
99 class SimpleT0Test(SimpleRegisterTest
):
101 self
.check_reg("t0", "x5")
103 class SimpleT1Test(SimpleRegisterTest
):
105 self
.check_reg("t1", "x6")
107 class SimpleF18Test(SimpleRegisterTest
):
108 def check_reg(self
, name
, alias
):
109 self
.gdb
.p_raw("$mstatus=$mstatus | 0x00006000")
113 self
.gdb
.p_raw("$%s=%f" % (name
, a
))
114 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
116 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - a
), .001)
117 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
118 self
.gdb
.p_raw("$%s=%f" % (alias
, b
))
119 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
121 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
122 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - b
), .001)
124 def early_applicable(self
):
125 return self
.hart
.extensionSupported('F')
128 self
.check_reg("f18", "fs2")
130 class SimpleMemoryTest(GdbTest
):
131 def access_test(self
, size
, data_type
):
132 assertEqual(self
.gdb
.p("sizeof(%s)" % data_type
), size
)
133 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
134 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
135 addrA
= self
.hart
.ram
136 addrB
= self
.hart
.ram
+ self
.hart
.ram_size
- size
137 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrA
, a
))
138 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrB
, b
))
139 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrA
)), a
)
140 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrB
)), b
)
142 class MemTest8(SimpleMemoryTest
):
144 self
.access_test(1, 'char')
146 class MemTest16(SimpleMemoryTest
):
148 self
.access_test(2, 'short')
150 class MemTest32(SimpleMemoryTest
):
152 self
.access_test(4, 'int')
154 class MemTest64(SimpleMemoryTest
):
156 self
.access_test(8, 'long long')
158 # FIXME: I'm not passing back invalid addresses correctly in read/write memory.
159 #class MemTestReadInvalid(SimpleMemoryTest):
161 # # This test relies on 'gdb_report_data_abort enable' being executed in
162 # # the openocd.cfg file.
164 # self.gdb.p("*((int*)0xdeadbeef)")
165 # assert False, "Read should have failed."
166 # except testlib.CannotAccess as e:
167 # assertEqual(e.address, 0xdeadbeef)
168 # self.gdb.p("*((int*)0x%x)" % self.hart.ram)
170 #class MemTestWriteInvalid(SimpleMemoryTest):
172 # # This test relies on 'gdb_report_data_abort enable' being executed in
173 # # the openocd.cfg file.
175 # self.gdb.p("*((int*)0xdeadbeef)=8675309")
176 # assert False, "Write should have failed."
177 # except testlib.CannotAccess as e:
178 # assertEqual(e.address, 0xdeadbeef)
179 # self.gdb.p("*((int*)0x%x)=6874742" % self.hart.ram)
181 class MemTestBlock(GdbTest
):
186 a
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
188 for i
in range(self
.length
/ self
.line_length
):
189 line_data
= "".join(["%c" % random
.randrange(256)
190 for _
in range(self
.line_length
)])
192 a
.write(ihex_line(i
* self
.line_length
, 0, line_data
))
195 self
.gdb
.command("shell cat %s" % a
.name
)
196 self
.gdb
.command("restore %s 0x%x" % (a
.name
, self
.hart
.ram
))
198 for offset
in range(0, self
.length
, increment
) + [self
.length
-4]:
199 value
= self
.gdb
.p("*((int*)0x%x)" % (self
.hart
.ram
+ offset
))
200 written
= ord(data
[offset
]) | \
201 (ord(data
[offset
+1]) << 8) | \
202 (ord(data
[offset
+2]) << 16) | \
203 (ord(data
[offset
+3]) << 24)
204 assertEqual(value
, written
)
206 b
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
207 self
.gdb
.command("dump ihex memory %s 0x%x 0x%x" % (b
.name
,
208 self
.hart
.ram
, self
.hart
.ram
+ self
.length
))
209 self
.gdb
.command("shell cat %s" % b
.name
)
210 for line
in b
.xreadlines():
211 record_type
, address
, line_data
= ihex_parse(line
)
213 written_data
= data
[address
:address
+len(line_data
)]
214 if line_data
!= written_data
:
216 "Data mismatch at 0x%x; wrote %s but read %s" % (
217 address
, readable_binary_string(written_data
),
218 readable_binary_string(line_data
)))
220 class InstantHaltTest(GdbTest
):
222 """Assert that reset is really resetting what it should."""
223 self
.gdb
.command("monitor reset halt")
224 self
.gdb
.command("flushregs")
225 threads
= self
.gdb
.threads()
229 pcs
.append(self
.gdb
.p("$pc"))
231 assertIn(pc
, self
.hart
.reset_vectors
)
232 # mcycle and minstret have no defined reset value.
233 mstatus
= self
.gdb
.p("$mstatus")
234 assertEqual(mstatus
& (MSTATUS_MIE | MSTATUS_MPRV |
237 class InstantChangePc(GdbTest
):
239 """Change the PC right as we come out of reset."""
241 self
.gdb
.command("monitor reset halt")
242 self
.gdb
.command("flushregs")
243 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
244 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
245 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
246 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
248 assertEqual((self
.hart
.ram
+ 4), self
.gdb
.p("$pc"))
250 assertEqual((self
.hart
.ram
+ 8), self
.gdb
.p("$pc"))
252 class DebugTest(GdbSingleHartTest
):
253 # Include malloc so that gdb can make function calls. I suspect this malloc
254 # will silently blow through the memory set aside for it, so be careful.
255 compile_args
= ("programs/debug.c", "programs/checksum.c",
256 "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
262 def exit(self
, expected_result
=0xc86455d4):
263 output
= self
.gdb
.c()
264 assertIn("Breakpoint", output
)
265 assertIn("_exit", output
)
266 assertEqual(self
.gdb
.p("status"), expected_result
)
268 class DebugCompareSections(DebugTest
):
270 output
= self
.gdb
.command("compare-sections")
272 for line
in output
.splitlines():
273 if line
.startswith("Section"):
274 assert line
.endswith("matched.")
276 assertGreater(matched
, 1)
278 class DebugFunctionCall(DebugTest
):
280 self
.gdb
.b("main:start")
282 assertEqual(self
.gdb
.p('fib(6)'), 8)
283 assertEqual(self
.gdb
.p('fib(7)'), 13)
286 class DebugChangeString(DebugTest
):
288 text
= "This little piggy went to the market."
289 self
.gdb
.b("main:start")
291 self
.gdb
.p('fox = "%s"' % text
)
292 self
.exit(0x43b497b8)
294 class DebugTurbostep(DebugTest
):
296 """Single step a bunch of times."""
297 self
.gdb
.b("main:start")
299 self
.gdb
.command("p i=0")
305 pc
= self
.gdb
.p("$pc")
306 assertNotEqual(last_pc
, pc
)
307 if last_pc
and pc
> last_pc
and pc
- last_pc
<= 4:
312 # Some basic sanity that we're not running between breakpoints or
314 assertGreater(jumps
, 1)
315 assertGreater(advances
, 5)
317 class DebugExit(DebugTest
):
321 class DebugSymbols(DebugTest
):
325 output
= self
.gdb
.c()
326 assertIn(", main ", output
)
327 output
= self
.gdb
.c()
328 assertIn(", rot13 ", output
)
330 class DebugBreakpoint(DebugTest
):
333 # The breakpoint should be hit exactly 2 times.
335 output
= self
.gdb
.c()
337 assertIn("Breakpoint ", output
)
338 assertIn("rot13 ", output
)
341 class Hwbp1(DebugTest
):
343 if self
.hart
.instruction_hardware_breakpoint_count
< 1:
344 return 'not_applicable'
346 if not self
.hart
.honors_tdata1_hmode
:
347 # Run to main before setting the breakpoint, because startup code
348 # will otherwise clear the trigger that we set.
352 self
.gdb
.hbreak("rot13")
353 # The breakpoint should be hit exactly 2 times.
355 output
= self
.gdb
.c()
357 assertRegexpMatches(output
, r
"[bB]reakpoint")
358 assertIn("rot13 ", output
)
361 class Hwbp2(DebugTest
):
363 if self
.hart
.instruction_hardware_breakpoint_count
< 2:
364 return 'not_applicable'
366 self
.gdb
.hbreak("main")
367 self
.gdb
.hbreak("rot13")
368 # We should hit 3 breakpoints.
369 for expected
in ("main", "rot13", "rot13"):
370 output
= self
.gdb
.c()
372 assertRegexpMatches(output
, r
"[bB]reakpoint")
373 assertIn("%s " % expected
, output
)
376 class TooManyHwbp(DebugTest
):
379 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
381 output
= self
.gdb
.c()
382 assertIn("Cannot insert hardware breakpoint", output
)
383 # Clean up, otherwise the hardware breakpoints stay set and future
385 self
.gdb
.command("D")
387 class Registers(DebugTest
):
389 # Get to a point in the code where some registers have actually been
394 # Try both forms to test gdb.
395 for cmd
in ("info all-registers", "info registers all"):
396 output
= self
.gdb
.command(cmd
)
397 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
398 assertIn(reg
, output
)
399 for line
in output
.splitlines():
400 assertRegexpMatches(line
, r
"^\S")
403 # mcpuid is one of the few registers that should have the high bit set
405 # Leave this commented out until gdb and spike agree on the encoding of
406 # mcpuid (which is going to be renamed to misa in any case).
407 #assertRegexpMatches(output, ".*mcpuid *0x80")
410 # The instret register should always be changing.
413 # instret = self.gdb.p("$instret")
414 # assertNotEqual(instret, last_instret)
415 # last_instret = instret
420 class UserInterrupt(DebugTest
):
422 """Sending gdb ^C while the program is running should cause it to
424 self
.gdb
.b("main:start")
427 self
.gdb
.c(wait
=False)
429 output
= self
.gdb
.interrupt()
430 assert "main" in output
431 assertGreater(self
.gdb
.p("j"), 10)
435 class InterruptTest(GdbSingleHartTest
):
436 compile_args
= ("programs/interrupt.c",)
438 def early_applicable(self
):
439 return self
.target
.supports_clint_mtime
446 output
= self
.gdb
.c()
447 assertIn(" main ", output
)
448 self
.gdb
.b("trap_entry")
449 output
= self
.gdb
.c()
450 assertIn(" trap_entry ", output
)
451 assertEqual(self
.gdb
.p("$mip") & 0x80, 0x80)
452 assertEqual(self
.gdb
.p("interrupt_count"), 0)
453 # You'd expect local to still be 0, but it looks like spike doesn't
454 # jump to the interrupt handler immediately after the write to
456 assertLess(self
.gdb
.p("local"), 1000)
457 self
.gdb
.command("delete breakpoints")
459 self
.gdb
.c(wait
=False)
462 interrupt_count
= self
.gdb
.p("interrupt_count")
463 local
= self
.gdb
.p("local")
464 if interrupt_count
> 1000 and \
468 assertGreater(interrupt_count
, 1000)
469 assertGreater(local
, 1000)
471 def postMortem(self
):
472 GdbSingleHartTest
.postMortem(self
)
473 self
.gdb
.p("*((long long*) 0x200bff8)")
474 self
.gdb
.p("*((long long*) 0x2004000)")
475 self
.gdb
.p("interrupt_count")
478 class MulticoreRegTest(GdbTest
):
479 compile_args
= ("programs/infinite_loop.S", "-DMULTICORE")
481 def early_applicable(self
):
482 return len(self
.target
.harts
) > 1
486 for hart
in self
.target
.harts
:
487 self
.gdb
.select_hart(hart
)
488 self
.gdb
.p("$pc=_start")
492 for hart
in self
.target
.harts
:
493 self
.gdb
.select_hart(hart
)
496 assertIn("main", self
.gdb
.where())
497 self
.gdb
.command("delete breakpoints")
499 # Run through the entire loop.
500 for hart
in self
.target
.harts
:
501 self
.gdb
.select_hart(hart
)
502 self
.gdb
.b("main_end")
504 assertIn("main_end", self
.gdb
.where())
507 for hart
in self
.target
.harts
:
508 self
.gdb
.select_hart(hart
)
509 # Check register values.
510 hart_id
= self
.gdb
.p("$x1")
511 assertNotIn(hart_id
, hart_ids
)
512 hart_ids
.append(hart_id
)
513 for n
in range(2, 32):
514 value
= self
.gdb
.p("$x%d" % n
)
515 assertEqual(value
, hart_ids
[-1] + n
- 1)
517 # Confirmed that we read different register values for different harts.
518 # Write a new value to x1, and run through the add sequence again.
520 for hart
in self
.target
.harts
:
521 self
.gdb
.select_hart(hart
)
522 self
.gdb
.p("$x1=0x%x" % (hart
.index
* 0x800))
523 self
.gdb
.p("$pc=main_post_csrr")
525 for hart
in self
.target
.harts
:
526 self
.gdb
.select_hart(hart
)
527 assertIn("main", self
.gdb
.where())
528 # Check register values.
529 for n
in range(1, 32):
530 value
= self
.gdb
.p("$x%d" % n
)
531 assertEqual(value
, hart
.index
* 0x800 + n
- 1)
533 class MulticoreRunHaltStepiTest(GdbTest
):
534 compile_args
= ("programs/multicore.c", "-DMULTICORE")
536 def early_applicable(self
):
537 return len(self
.target
.harts
) > 1
541 for hart
in self
.target
.harts
:
542 self
.gdb
.select_hart(hart
)
543 self
.gdb
.p("$pc=_start")
546 previous_hart_count
= [0 for h
in self
.target
.harts
]
547 previous_interrupt_count
= [0 for h
in self
.target
.harts
]
549 self
.gdb
.c(wait
=False)
554 self
.gdb
.p("$mstatus")
556 self
.gdb
.p("buf", fmt
="")
557 hart_count
= self
.gdb
.p("hart_count")
558 interrupt_count
= self
.gdb
.p("interrupt_count")
559 for i
, h
in enumerate(self
.target
.harts
):
560 assertGreater(hart_count
[i
], previous_hart_count
[i
])
561 assertGreater(interrupt_count
[i
], previous_interrupt_count
[i
])
562 self
.gdb
.select_hart(h
)
563 pc
= self
.gdb
.p("$pc")
565 stepped_pc
= self
.gdb
.p("$pc")
566 assertNotEqual(pc
, stepped_pc
)
568 class StepTest(GdbTest
):
569 compile_args
= ("programs/step.S", )
577 main_address
= self
.gdb
.p("$pc")
578 if self
.hart
.extensionSupported("c"):
579 sequence
= (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24)
581 sequence
= (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c)
582 for expected
in sequence
:
584 pc
= self
.gdb
.p("$pc")
585 assertEqual("%x" % (pc
- main_address
), "%x" % expected
)
587 class TriggerTest(GdbTest
):
588 compile_args
= ("programs/trigger.S", )
596 output
= self
.gdb
.c()
597 assertIn("Breakpoint", output
)
598 assertIn("_exit", output
)
600 class TriggerExecuteInstant(TriggerTest
):
601 """Test an execute breakpoint on the first instruction executed out of
604 main_address
= self
.gdb
.p("$pc")
605 self
.gdb
.command("hbreak *0x%x" % (main_address
+ 4))
607 assertEqual(self
.gdb
.p("$pc"), main_address
+4)
609 # FIXME: Triggers aren't quite working yet
610 #class TriggerLoadAddress(TriggerTest):
612 # self.gdb.command("rwatch *((&data)+1)")
613 # output = self.gdb.c()
614 # assertIn("read_loop", output)
615 # assertEqual(self.gdb.p("$a0"),
616 # self.gdb.p("(&data)+1"))
619 class TriggerLoadAddressInstant(TriggerTest
):
620 """Test a load address breakpoint on the first instruction executed out of
623 self
.gdb
.command("b just_before_read_loop")
625 read_loop
= self
.gdb
.p("&read_loop")
626 self
.gdb
.command("rwatch data")
628 # Accept hitting the breakpoint before or after the load instruction.
629 assertIn(self
.gdb
.p("$pc"), [read_loop
, read_loop
+ 4])
630 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
632 # FIXME: Triggers aren't quite working yet
633 #class TriggerStoreAddress(TriggerTest):
635 # self.gdb.command("watch *((&data)+3)")
636 # output = self.gdb.c()
637 # assertIn("write_loop", output)
638 # assertEqual(self.gdb.p("$a0"),
639 # self.gdb.p("(&data)+3"))
642 class TriggerStoreAddressInstant(TriggerTest
):
644 """Test a store address breakpoint on the first instruction executed out
646 self
.gdb
.command("b just_before_write_loop")
648 write_loop
= self
.gdb
.p("&write_loop")
649 self
.gdb
.command("watch data")
651 # Accept hitting the breakpoint before or after the store instruction.
652 assertIn(self
.gdb
.p("$pc"), [write_loop
, write_loop
+ 4])
653 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
655 class TriggerDmode(TriggerTest
):
656 def early_applicable(self
):
657 return self
.hart
.honors_tdata1_hmode
659 def check_triggers(self
, tdata1_lsbs
, tdata2
):
660 dmode
= 1 << (self
.hart
.xlen
-5)
664 if self
.hart
.xlen
== 32:
666 elif self
.hart
.xlen
== 64:
667 xlen_type
= 'long long'
669 raise NotImplementedError
674 tdata1
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
))
677 tdata2
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
+1))
682 assertEqual(tdata1
& 0xffff, tdata1_lsbs
)
683 assertEqual(tdata2
, tdata2
)
686 assertEqual(dmode_count
, 1)
691 self
.gdb
.command("hbreak write_load_trigger")
692 self
.gdb
.b("clear_triggers")
693 self
.gdb
.p("$pc=write_store_trigger")
694 output
= self
.gdb
.c()
695 assertIn("write_load_trigger", output
)
696 self
.check_triggers((1<<6) |
(1<<1), 0xdeadbee0)
697 output
= self
.gdb
.c()
698 assertIn("clear_triggers", output
)
699 self
.check_triggers((1<<6) |
(1<<0), 0xfeedac00)
701 class RegsTest(GdbTest
):
702 compile_args
= ("programs/regs.S", )
706 self
.gdb
.b("handle_trap")
709 class WriteGprs(RegsTest
):
711 regs
= [("x%d" % n
) for n
in range(2, 32)]
713 self
.gdb
.p("$pc=write_regs")
714 for i
, r
in enumerate(regs
):
715 self
.gdb
.p("$%s=%d" % (r
, (0xdeadbeef<<i
)+17))
716 self
.gdb
.p("$x1=data")
717 self
.gdb
.command("b all_done")
718 output
= self
.gdb
.c()
719 assertIn("Breakpoint ", output
)
721 # Just to get this data in the log.
722 self
.gdb
.command("x/30gx data")
723 self
.gdb
.command("info registers")
724 for n
in range(len(regs
)):
725 assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
726 ((0xdeadbeef<<n
)+17) & ((1<<self
.hart
.xlen
)-1))
728 class WriteCsrs(RegsTest
):
730 # As much a test of gdb as of the simulator.
731 self
.gdb
.p("$mscratch=0")
733 assertEqual(self
.gdb
.p("$mscratch"), 0)
734 self
.gdb
.p("$mscratch=123")
736 assertEqual(self
.gdb
.p("$mscratch"), 123)
738 self
.gdb
.p("$pc=write_regs")
739 self
.gdb
.p("$x1=data")
740 self
.gdb
.command("b all_done")
741 self
.gdb
.command("c")
743 assertEqual(123, self
.gdb
.p("$mscratch"))
744 assertEqual(123, self
.gdb
.p("$x1"))
745 assertEqual(123, self
.gdb
.p("$csr832"))
747 class DownloadTest(GdbTest
):
749 # pylint: disable=attribute-defined-outside-init
750 length
= min(2**10, self
.hart
.ram_size
- 2048)
751 self
.download_c
= tempfile
.NamedTemporaryFile(prefix
="download_",
752 suffix
=".c", delete
=False)
753 self
.download_c
.write("#include <stdint.h>\n")
754 self
.download_c
.write(
755 "unsigned int crc32a(uint8_t *message, unsigned int size);\n")
756 self
.download_c
.write("uint32_t length = %d;\n" % length
)
757 self
.download_c
.write("uint8_t d[%d] = {\n" % length
)
759 assert length
% 16 == 0
760 for i
in range(length
/ 16):
761 self
.download_c
.write(" /* 0x%04x */ " % (i
* 16))
763 value
= random
.randrange(1<<8)
764 self
.download_c
.write("0x%02x, " % value
)
765 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
766 self
.download_c
.write("\n")
767 self
.download_c
.write("};\n")
768 self
.download_c
.write("uint8_t *data = &d[0];\n")
769 self
.download_c
.write(
770 "uint32_t main() { return crc32a(data, length); }\n")
771 self
.download_c
.flush()
776 self
.binary
= self
.target
.compile(self
.hart
, self
.download_c
.name
,
777 "programs/checksum.c")
778 self
.gdb
.command("file %s" % self
.binary
)
782 self
.gdb
.command("b _exit")
783 self
.gdb
.c(timeout
=60)
784 assertEqual(self
.gdb
.p("status"), self
.crc
)
785 os
.unlink(self
.download_c
.name
)
787 #class MprvTest(GdbTest):
788 # compile_args = ("programs/mprv.S", )
793 # """Test that the debugger can access memory when MPRV is set."""
794 # self.gdb.c(wait=False)
796 # self.gdb.interrupt()
797 # output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)")
798 # assertIn("0xbead", output)
800 class PrivTest(GdbTest
):
801 compile_args
= ("programs/priv.S", )
803 # pylint: disable=attribute-defined-outside-init
806 misa
= self
.hart
.misa
807 self
.supported
= set()
809 self
.supported
.add(0)
811 self
.supported
.add(1)
813 self
.supported
.add(2)
814 self
.supported
.add(3)
816 class PrivRw(PrivTest
):
818 """Test reading/writing priv."""
819 # Disable physical memory protection by allowing U mode access to all
821 self
.gdb
.p("$pmpcfg0=0xf") # TOR, R, W, X
822 self
.gdb
.p("$pmpaddr0=0x%x" %
823 ((self
.hart
.ram
+ self
.hart
.ram_size
) >> 2))
825 # Leave the PC at _start, where the first 4 instructions should be
827 for privilege
in range(4):
828 self
.gdb
.p("$priv=%d" % privilege
)
830 actual
= self
.gdb
.p("$priv")
831 assertIn(actual
, self
.supported
)
832 if privilege
in self
.supported
:
833 assertEqual(actual
, privilege
)
835 class PrivChange(PrivTest
):
837 """Test that the core's privilege level actually changes."""
839 if 0 not in self
.supported
:
840 return 'not_applicable'
846 self
.gdb
.p("$priv=3")
847 main_address
= self
.gdb
.p("$pc")
849 assertEqual("%x" % self
.gdb
.p("$pc"), "%x" % (main_address
+4))
852 self
.gdb
.p("$priv=0")
854 # Should have taken an exception, so be nowhere near main.
855 pc
= self
.gdb
.p("$pc")
856 assertTrue(pc
< main_address
or pc
> main_address
+ 0x100)
860 parser
= argparse
.ArgumentParser(
861 description
="Test that gdb can talk to a RISC-V target.",
863 Example command line from the real world:
864 Run all RegsTest cases against a physical FPGA, with custom openocd command:
865 ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
867 targets
.add_target_options(parser
)
869 testlib
.add_test_run_options(parser
)
871 # TODO: remove global
872 global parsed
# pylint: disable=global-statement
873 parsed
= parser
.parse_args()
874 target
= targets
.target(parsed
)
875 testlib
.print_log_names
= parsed
.print_log_names
877 module
= sys
.modules
[__name__
]
879 return testlib
.run_all_tests(module
, target
, parsed
)
881 # TROUBLESHOOTING TIPS
882 # If a particular test fails, run just that one test, eg.:
883 # ./gdbserver.py MprvTest.test_mprv
884 # Then inspect gdb.log and spike.log to see what happened in more detail.
886 if __name__
== '__main__':