isa/macros/scalar/test_macros.h

   1 #ifndef __TEST_MACROS_SCALAR_H
   2 #define __TEST_MACROS_SCALAR_H
   3
   4
   5 #-----------------------------------------------------------------------
   6 # Helper macros
   7 #-----------------------------------------------------------------------
   8
   9 #define TEST_CASE( testnum, testreg, correctval, code... ) \
  10 test_ ## testnum: \
  11     code; \
  12     li  x29, correctval; \
  13     li  x28, testnum; \
  14     bne testreg, x29, fail;
  15
  16 #define TEST_CASE_JUMP( testnum, testreg, correctval, code... ) \
  17 test_ ## testnum: \
  18     code; \
  19     li  x29, correctval; \
  20     li  x28, testnum; \
  21     beq testreg, x29, pass_ ## testnum; \
  22     j fail; \
  23 pass_ ## testnum: \
  24
  25 # We use a macro hack to simpify code generation for various numbers
  26 # of bubble cycles.
  27
  28 #define TEST_INSERT_NOPS_0
  29 #define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
  30 #define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
  31 #define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
  32 #define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
  33 #define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
  34 #define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
  35 #define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
  36 #define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
  37 #define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
  38 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
  39
  40
  41 #-----------------------------------------------------------------------
  42 # RV64UI MACROS
  43 #-----------------------------------------------------------------------
  44
  45 #-----------------------------------------------------------------------
  46 # Tests for instructions with immediate operand
  47 #-----------------------------------------------------------------------
  48
  49 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
  50     TEST_CASE( testnum, x3, result, \
  51       li  x1, val1; \
  52       inst x3, x1, imm; \
  53     )
  54
  55 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
  56     TEST_CASE( testnum, x1, result, \
  57       li  x1, val1; \
  58       inst x1, x1, imm; \
  59     )
  60
  61 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  62     TEST_CASE( testnum, x6, result, \
  63       li  x4, 0; \
  64 1:    li  x1, val1; \
  65       inst x3, x1, imm; \
  66       TEST_INSERT_NOPS_ ## nop_cycles \
  67       addi  x6, x3, 0; \
  68       addi  x4, x4, 1; \
  69       li  x5, 2; \
  70       bne x4, x5, 1b \
  71     )
  72
  73 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  74     TEST_CASE( testnum, x3, result, \
  75       li  x4, 0; \
  76 1:    li  x1, val1; \
  77       TEST_INSERT_NOPS_ ## nop_cycles \
  78       inst x3, x1, imm; \
  79       addi  x4, x4, 1; \
  80       li  x5, 2; \
  81       bne x4, x5, 1b \
  82     )
  83
  84 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
  85     TEST_CASE( testnum, x1, result, \
  86       inst x1, x0, imm; \
  87     )
  88
  89 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
  90     TEST_CASE( testnum, x0, 0, \
  91       li  x1, val1; \
  92       inst x0, x1, imm; \
  93     )
  94
  95 #-----------------------------------------------------------------------
  96 # Tests for vector config instructions
  97 #-----------------------------------------------------------------------
  98
  99 #define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
 100     TEST_CASE_JUMP( testnum, x1, result, \
 101       li x1, (bank << 12); \
 102       vsetcfg x1,nxpr,nfpr; \
 103       li x1, vl; \
 104       vsetvl x1,x1; \
 105     )
 106
 107 #define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
 108     TEST_CASE_JUMP( testnum, x1, result, \
 109       li x1, (bank << 12) | (nfpr << 6) | nxpr; \
 110       vsetcfg x1; \
 111       li x1, vl; \
 112       vsetvl x1,x1; \
 113     )
 114
 115 #define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
 116     TEST_CASE_JUMP( testnum, x1, result, \
 117       li x1, (bank << 12); \
 118       vsetcfg x1,nxpr,nfpr; \
 119       li x1, vl; \
 120       vsetvl x1, x1; \
 121     )
 122
 123 #-----------------------------------------------------------------------
 124 # Tests for an instruction with register operands
 125 #-----------------------------------------------------------------------
 126
 127 #define TEST_R_OP( testnum, inst, result, val1 ) \
 128     TEST_CASE( testnum, x3, result, \
 129       li  x1, val1; \
 130       inst x3, x1; \
 131     )
 132
 133 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
 134     TEST_CASE( testnum, x1, result, \
 135       li  x1, val1; \
 136       inst x1, x1; \
 137     )
 138
 139 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
 140     TEST_CASE( testnum, x6, result, \
 141       li  x4, 0; \
 142 1:    li  x1, val1; \
 143       inst x3, x1; \
 144       TEST_INSERT_NOPS_ ## nop_cycles \
 145       addi  x6, x3, 0; \
 146       addi  x4, x4, 1; \
 147       li  x5, 2; \
 148       bne x4, x5, 1b \
 149     )
 150
 151 #-----------------------------------------------------------------------
 152 # Tests for an instruction with register-register operands
 153 #-----------------------------------------------------------------------
 154
 155 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
 156     TEST_CASE( testnum, x3, result, \
 157       li  x1, val1; \
 158       li  x2, val2; \
 159       inst x3, x1, x2; \
 160     )
 161
 162 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
 163     TEST_CASE( testnum, x1, result, \
 164       li  x1, val1; \
 165       li  x2, val2; \
 166       inst x1, x1, x2; \
 167     )
 168
 169 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
 170     TEST_CASE( testnum, x2, result, \
 171       li  x1, val1; \
 172       li  x2, val2; \
 173       inst x2, x1, x2; \
 174     )
 175
 176 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
 177     TEST_CASE( testnum, x1, result, \
 178       li  x1, val1; \
 179       inst x1, x1, x1; \
 180     )
 181
 182 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
 183     TEST_CASE( testnum, x6, result, \
 184       li  x4, 0; \
 185 1:    li  x1, val1; \
 186       li  x2, val2; \
 187       inst x3, x1, x2; \
 188       TEST_INSERT_NOPS_ ## nop_cycles \
 189       addi  x6, x3, 0; \
 190       addi  x4, x4, 1; \
 191       li  x5, 2; \
 192       bne x4, x5, 1b \
 193     )
 194
 195 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 196     TEST_CASE( testnum, x3, result, \
 197       li  x4, 0; \
 198 1:    li  x1, val1; \
 199       TEST_INSERT_NOPS_ ## src1_nops \
 200       li  x2, val2; \
 201       TEST_INSERT_NOPS_ ## src2_nops \
 202       inst x3, x1, x2; \
 203       addi  x4, x4, 1; \
 204       li  x5, 2; \
 205       bne x4, x5, 1b \
 206     )
 207
 208 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 209     TEST_CASE( testnum, x3, result, \
 210       li  x4, 0; \
 211 1:    li  x2, val2; \
 212       TEST_INSERT_NOPS_ ## src1_nops \
 213       li  x1, val1; \
 214       TEST_INSERT_NOPS_ ## src2_nops \
 215       inst x3, x1, x2; \
 216       addi  x4, x4, 1; \
 217       li  x5, 2; \
 218       bne x4, x5, 1b \
 219     )
 220
 221 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
 222     TEST_CASE( testnum, x2, result, \
 223       li x1, val; \
 224       inst x2, x0, x1; \
 225     )
 226
 227 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
 228     TEST_CASE( testnum, x2, result, \
 229       li x1, val; \
 230       inst x2, x1, x0; \
 231     )
 232
 233 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
 234     TEST_CASE( testnum, x1, result, \
 235       inst x1, x0, x0; \
 236     )
 237
 238 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
 239     TEST_CASE( testnum, x0, 0, \
 240       li x1, val1; \
 241       li x2, val2; \
 242       inst x0, x1, x2; \
 243     )
 244
 245 #-----------------------------------------------------------------------
 246 # Test memory instructions
 247 #-----------------------------------------------------------------------
 248
 249 #define TEST_LD_OP( testnum, inst, result, offset, base ) \
 250     TEST_CASE( testnum, x3, result, \
 251       la  x1, base; \
 252       inst x3, offset(x1); \
 253     )
 254
 255 #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
 256     TEST_CASE( testnum, x3, result, \
 257       la  x1, base; \
 258       li  x2, result; \
 259       store_inst x2, offset(x1); \
 260       load_inst x3, offset(x1); \
 261     )
 262
 263 #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 264 test_ ## testnum: \
 265     li  x28, testnum; \
 266     li  x4, 0; \
 267 1:  la  x1, base; \
 268     inst x3, offset(x1); \
 269     TEST_INSERT_NOPS_ ## nop_cycles \
 270     addi  x6, x3, 0; \
 271     li  x29, result; \
 272     bne x6, x29, fail; \
 273     addi  x4, x4, 1; \
 274     li  x5, 2; \
 275     bne x4, x5, 1b; \
 276
 277 #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 278 test_ ## testnum: \
 279     li  x28, testnum; \
 280     li  x4, 0; \
 281 1:  la  x1, base; \
 282     TEST_INSERT_NOPS_ ## nop_cycles \
 283     inst x3, offset(x1); \
 284     li  x29, result; \
 285     bne x3, x29, fail; \
 286     addi  x4, x4, 1; \
 287     li  x5, 2; \
 288     bne x4, x5, 1b \
 289
 290 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 291 test_ ## testnum: \
 292     li  x28, testnum; \
 293     li  x4, 0; \
 294 1:  la  x1, result; \
 295     TEST_INSERT_NOPS_ ## src1_nops \
 296     la  x2, base; \
 297     TEST_INSERT_NOPS_ ## src2_nops \
 298     store_inst x1, offset(x2); \
 299     load_inst x3, offset(x2); \
 300     li  x29, result; \
 301     bne x3, x29, fail; \
 302     addi  x4, x4, 1; \
 303     li  x5, 2; \
 304     bne x4, x5, 1b \
 305
 306 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 307 test_ ## testnum: \
 308     li  x28, testnum; \
 309     li  x4, 0; \
 310 1:  la  x2, base; \
 311     TEST_INSERT_NOPS_ ## src1_nops \
 312     la  x1, result; \
 313     TEST_INSERT_NOPS_ ## src2_nops \
 314     store_inst x1, offset(x2); \
 315     load_inst x3, offset(x2); \
 316     li  x29, result; \
 317     bne x3, x29, fail; \
 318     addi  x4, x4, 1; \
 319     li  x5, 2; \
 320     bne x4, x5, 1b \
 321
 322 #-----------------------------------------------------------------------
 323 # Test branch instructions
 324 #-----------------------------------------------------------------------
 325
 326 #define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
 327 test_ ## testnum: \
 328     li  x28, testnum; \
 329     li  x1, val1; \
 330     inst x1, 2f; \
 331     bne x0, x28, fail; \
 332 1:  bne x0, x28, 3f; \
 333 2:  inst x1, 1b; \
 334     bne x0, x28, fail; \
 335 3:
 336
 337 #define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
 338 test_ ## testnum: \
 339     li  x28, testnum; \
 340     li  x1, val1; \
 341     inst x1, 1f; \
 342     bne x0, x28, 2f; \
 343 1:  bne x0, x28, fail; \
 344 2:  inst x1, 1b; \
 345 3:
 346
 347 #define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
 348 test_ ## testnum: \
 349     li  x28, testnum; \
 350     li  x4, 0; \
 351 1:  li  x1, val1; \
 352     TEST_INSERT_NOPS_ ## nop_cycles \
 353     inst x1, fail; \
 354     addi  x4, x4, 1; \
 355     li  x5, 2; \
 356     bne x4, x5, 1b \
 357
 358 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
 359 test_ ## testnum: \
 360     li  x28, testnum; \
 361     li  x1, val1; \
 362     li  x2, val2; \
 363     inst x1, x2, 2f; \
 364     bne x0, x28, fail; \
 365 1:  bne x0, x28, 3f; \
 366 2:  inst x1, x2, 1b; \
 367     bne x0, x28, fail; \
 368 3:
 369
 370 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 371 test_ ## testnum: \
 372     li  x28, testnum; \
 373     li  x1, val1; \
 374     li  x2, val2; \
 375     inst x1, x2, 1f; \
 376     bne x0, x28, 2f; \
 377 1:  bne x0, x28, fail; \
 378 2:  inst x1, x2, 1b; \
 379 3:
 380
 381 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 382 test_ ## testnum: \
 383     li  x28, testnum; \
 384     li  x4, 0; \
 385 1:  li  x1, val1; \
 386     TEST_INSERT_NOPS_ ## src1_nops \
 387     li  x2, val2; \
 388     TEST_INSERT_NOPS_ ## src2_nops \
 389     inst x1, x2, fail; \
 390     addi  x4, x4, 1; \
 391     li  x5, 2; \
 392     bne x4, x5, 1b \
 393
 394 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 395 test_ ## testnum: \
 396     li  x28, testnum; \
 397     li  x4, 0; \
 398 1:  li  x2, val2; \
 399     TEST_INSERT_NOPS_ ## src1_nops \
 400     li  x1, val1; \
 401     TEST_INSERT_NOPS_ ## src2_nops \
 402     inst x1, x2, fail; \
 403     addi  x4, x4, 1; \
 404     li  x5, 2; \
 405     bne x4, x5, 1b \
 406
 407 #-----------------------------------------------------------------------
 408 # Test jump instructions
 409 #-----------------------------------------------------------------------
 410
 411 #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 412 test_ ## testnum: \
 413     li  x28, testnum; \
 414     li  x4, 0; \
 415 1:  la  x6, 2f; \
 416     TEST_INSERT_NOPS_ ## nop_cycles \
 417     inst x6; \
 418     bne x0, x28, fail; \
 419 2:  addi  x4, x4, 1; \
 420     li  x5, 2; \
 421     bne x4, x5, 1b \
 422
 423 #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 424 test_ ## testnum: \
 425     li  x28, testnum; \
 426     li  x4, 0; \
 427 1:  la  x6, 2f; \
 428     TEST_INSERT_NOPS_ ## nop_cycles \
 429     inst x19, x6, 0; \
 430     bne x0, x28, fail; \
 431 2:  addi  x4, x4, 1; \
 432     li  x5, 2; \
 433     bne x4, x5, 1b \
 434
 435
 436 #-----------------------------------------------------------------------
 437 # RV64UF MACROS
 438 #-----------------------------------------------------------------------
 439
 440 #-----------------------------------------------------------------------
 441 # Tests floating-point instructions
 442 #-----------------------------------------------------------------------
 443
 444 #define TEST_FP_OP_S_INTERNAL( testnum, result, val1, val2, val3, code... ) \
 445 test_ ## testnum: \
 446   li  x28, testnum; \
 447   la  a0, test_ ## testnum ## _data ;\
 448   flw f0, 0(a0); \
 449   flw f1, 4(a0); \
 450   flw f2, 8(a0); \
 451   lw  a3, 12(a0); \
 452   code; \
 453   bne a0, a3, fail; \
 454   b 1f; \
 455   .align 2; \
 456   test_ ## testnum ## _data: \
 457   .float val1; \
 458   .float val2; \
 459   .float val3; \
 460   .result; \
 461 1:
 462
 463 #define TEST_FP_OP_D_INTERNAL( testnum, result, val1, val2, val3, code... ) \
 464 test_ ## testnum: \
 465   li  x28, testnum; \
 466   la  a0, test_ ## testnum ## _data ;\
 467   fld f0, 0(a0); \
 468   fld f1, 8(a0); \
 469   fld f2, 16(a0); \
 470   ld  a3, 24(a0); \
 471   code; \
 472   bne a0, a3, fail; \
 473   b 1f; \
 474   .align 3; \
 475   test_ ## testnum ## _data: \
 476   .double val1; \
 477   .double val2; \
 478   .double val3; \
 479   .result; \
 480 1:
 481
 482 #define TEST_FCVT_S_D( testnum, result, val1 ) \
 483   TEST_FP_OP_D_INTERNAL( testnum, double result, val1, 0.0, 0.0, \
 484                     fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
 485
 486 #define TEST_FCVT_D_S( testnum, result, val1 ) \
 487   TEST_FP_OP_S_INTERNAL( testnum, float result, val1, 0.0, 0.0, \
 488                     fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
 489
 490 #define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
 491   TEST_FP_OP_S_INTERNAL( testnum, float result, val1, 0.0, 0.0, \
 492                     inst f3, f0; fmv.x.s a0, f3)
 493
 494 #define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
 495   TEST_FP_OP_D_INTERNAL( testnum, double result, val1, 0.0, 0.0, \
 496                     inst f3, f0; fmv.x.d a0, f3)
 497
 498 #define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
 499   TEST_FP_OP_S_INTERNAL( testnum, float result, val1, val2, 0.0, \
 500                     inst f3, f0, f1; fmv.x.s a0, f3)
 501
 502 #define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
 503   TEST_FP_OP_D_INTERNAL( testnum, double result, val1, val2, 0.0, \
 504                     inst f3, f0, f1; fmv.x.d a0, f3)
 505
 506 #define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
 507   TEST_FP_OP_S_INTERNAL( testnum, float result, val1, val2, val3, \
 508                     inst f3, f0, f1, f2; fmv.x.s a0, f3)
 509
 510 #define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
 511   TEST_FP_OP_D_INTERNAL( testnum, double result, val1, val2, val3, \
 512                     inst f3, f0, f1, f2; fmv.x.d a0, f3)
 513
 514 #define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
 515   TEST_FP_OP_S_INTERNAL( testnum, word result, val1, 0.0, 0.0, \
 516                     inst a0, f0, rm)
 517
 518 #define TEST_FP_INT_OP_D( testnum, inst, result, val1, rm ) \
 519   TEST_FP_OP_D_INTERNAL( testnum, dword result, val1, 0.0, 0.0, \
 520                     inst a0, f0, rm)
 521
 522 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
 523   TEST_FP_OP_S_INTERNAL( testnum, word result, val1, val2, 0.0, \
 524                     inst a0, f0, f1)
 525
 526 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
 527   TEST_FP_OP_D_INTERNAL( testnum, dword result, val1, val2, 0.0, \
 528                     inst a0, f0, f1)
 529
 530 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 531 test_ ## testnum: \
 532   li  x28, testnum; \
 533   la  a0, test_ ## testnum ## _data ;\
 534   lw  a3, 0(a0); \
 535   li  a0, val1; \
 536   inst f0, a0; \
 537   fmv.x.s a0, f0; \
 538   bne a0, a3, fail; \
 539   b 1f; \
 540   .align 2; \
 541   test_ ## testnum ## _data: \
 542   .float result; \
 543 1:
 544
 545 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 546 test_ ## testnum: \
 547   li  x28, testnum; \
 548   la  a0, test_ ## testnum ## _data ;\
 549   ld  a3, 0(a0); \
 550   li  a0, val1; \
 551   inst f0, a0; \
 552   fmv.x.d a0, f0; \
 553   bne a0, a3, fail; \
 554   b 1f; \
 555   .align 3; \
 556   test_ ## testnum ## _data: \
 557   .double result; \
 558 1:
 559
 560
 561 #-----------------------------------------------------------------------
 562 # RV64SV MACROS
 563 #-----------------------------------------------------------------------
 564
 565 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
 566   setpcr status, SR_EI; \
 567   la a0, handler ## testnum; \
 568   mtpcr a0, evec; \
 569   vsetcfg nxreg, nfreg; \
 570   li a0, 4; \
 571   vsetvl a0, a0; \
 572   la a0, src1; \
 573   la a1, src2; \
 574   vld vx2, a0; \
 575   vld vx3, a1; \
 576   lui a0,%hi(vtcode1 ## testnum); \
 577   vf %lo(vtcode1 ## testnum)(a0); \
 578   la reg2, dest; \
 579 illegal ## testnum: \
 580   inst reg1, reg2; \
 581   la a3, dest; \
 582   vsd vx2, a3; \
 583   fence; \
 584 vtcode1 ## testnum: \
 585   add x2, x2, x3; \
 586   stop; \
 587 vtcode2 ## testnum: \
 588   add x2, x2, x3; \
 589   stop; \
 590 handler ## testnum: \
 591   vxcptkill; \
 592   li x28,2; \
 593   vxcptcause a0; \
 594   li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
 595   bne a0,a1,fail; \
 596   vxcptaux a0; \
 597   la a1, illegal ## testnum; \
 598   lw a2, 0(a1); \
 599   bne a0, a2, fail; \
 600   vsetcfg 32,0; \
 601   li a0,4; \
 602   vsetvl a0,a0; \
 603   la a0,src1; \
 604   la a1,src2; \
 605   vld vx2,a0; \
 606   vld vx3,a1; \
 607   lui a0,%hi(vtcode2 ## testnum); \
 608   vf %lo(vtcode2 ## testnum)(a0); \
 609   la a3,dest; \
 610   vsd vx2,a3; \
 611   fence; \
 612   ld a1,0(a3); \
 613   li a2,5; \
 614   li x28,2; \
 615   bne a1,a2,fail; \
 616   ld a1,8(a3); \
 617   li x28,3; \
 618   bne a1,a2,fail; \
 619   ld a1,16(a3); \
 620   li x28,4; \
 621   bne a1,a2,fail; \
 622   ld a1,24(a3); \
 623   li x28,5; \
 624   bne a1,a2,fail; \
 625
 626 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
 627   setpcr status, SR_EI; \
 628   la a0, handler ## testnum; \
 629   mtpcr a0, evec; \
 630   vsetcfg nxreg, nfreg; \
 631   li a0, 4; \
 632   vsetvl a0, a0; \
 633   la a0, src1; \
 634   la a1, src2; \
 635   vld vx2, a0; \
 636   vld vx3, a1; \
 637   lui a0,%hi(vtcode1 ## testnum); \
 638   vf %lo(vtcode1 ## testnum)(a0); \
 639   la a3, dest; \
 640   vsd vx2, a3; \
 641   fence; \
 642 vtcode1 ## testnum: \
 643   add x2, x2, x3; \
 644 illegal ## testnum: \
 645   inst reg1, reg2, reg3; \
 646   stop; \
 647 vtcode2 ## testnum: \
 648   add x2, x2, x3; \
 649   stop; \
 650 handler ## testnum: \
 651   vxcptkill; \
 652   li x28,2; \
 653   vxcptcause a0; \
 654   li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
 655   bne a0,a1,fail; \
 656   vxcptaux a0; \
 657   la a1,illegal ## testnum; \
 658   bne a0,a1,fail; \
 659   vsetcfg 32,0; \
 660   li a0,4; \
 661   vsetvl a0,a0; \
 662   la a0,src1; \
 663   la a1,src2; \
 664   vld vx2,a0; \
 665   vld vx3,a1; \
 666   lui a0,%hi(vtcode2 ## testnum); \
 667   vf %lo(vtcode2 ## testnum)(a0); \
 668   la a3,dest; \
 669   vsd vx2,a3; \
 670   fence; \
 671   ld a1,0(a3); \
 672   li a2,5; \
 673   li x28,2; \
 674   bne a1,a2,fail; \
 675   ld a1,8(a3); \
 676   li x28,3; \
 677   bne a1,a2,fail; \
 678   ld a1,16(a3); \
 679   li x28,4; \
 680   bne a1,a2,fail; \
 681   ld a1,24(a3); \
 682   li x28,5; \
 683   bne a1,a2,fail; \
 684
 685 #-----------------------------------------------------------------------
 686 # Pass and fail code (assumes test num is in x28)
 687 #-----------------------------------------------------------------------
 688
 689 #define TEST_PASSFAIL \
 690         bne x0, x28, pass; \
 691 fail: \
 692         RVTEST_FAIL \
 693 pass: \
 694         RVTEST_PASS \
 695
 696
 697 #-----------------------------------------------------------------------
 698 # Test data section
 699 #-----------------------------------------------------------------------
 700
 701 #define TEST_DATA
 702
 703 #endif