isa/rv32si/ma_addr.S

   1 #*****************************************************************************
   2 # ma_addr.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test misaligned ld/st trap.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV32S
  12 RVTEST_CODE_BEGIN
  13
  14   la s0, evec_load
  15
  16   la t0, evec_load
  17   csrw evec, t0
  18
  19   li TESTNUM, 2
  20   lw x0, 1(s0)
  21   j fail
  22
  23   li TESTNUM, 3
  24   lw x0, 2(s0)
  25   j fail
  26
  27   li TESTNUM, 4
  28   lw x0, 3(s0)
  29   j fail
  30
  31   li TESTNUM, 5
  32   lh x0, 1(s0)
  33   j fail
  34
  35   li TESTNUM, 6
  36   lhu x0, 1(s0)
  37   j fail
  38
  39   la t0, evec_store
  40   csrw evec, t0
  41
  42   li TESTNUM, 7
  43   sw x0, 1(s0)
  44   j fail
  45
  46   li TESTNUM, 8
  47   sw x0, 2(s0)
  48   j fail
  49
  50   li TESTNUM, 9
  51   sw x0, 3(s0)
  52   j fail
  53
  54   li TESTNUM, 10
  55   sh x0, 1(s0)
  56   j fail
  57
  58   j pass
  59
  60   TEST_PASSFAIL
  61
  62 evec_load:
  63   li t1, CAUSE_MISALIGNED_LOAD
  64   csrr t0, cause
  65   bne t0, t1, fail
  66   csrr t0, epc
  67   addi t0, t0, 8
  68   csrw epc, t0
  69   sret
  70
  71 evec_store:
  72   li t1, CAUSE_MISALIGNED_STORE
  73   csrr t0, cause
  74   bne t0, t1, fail
  75   csrr t0, epc
  76   addi t0, t0, 8
  77   csrw epc, t0
  78   sret
  79
  80 RVTEST_CODE_END
  81
  82   .data
  83 RVTEST_DATA_BEGIN
  84
  85   TEST_DATA
  86
  87 RVTEST_DATA_END