Add LICENSE
[riscv-tests.git] / isa / rv64sv / illegal_cfg_nfpr.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal_tvec_cmd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal tvec command trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 li a0, SR_EA | SR_EI
17 csrs status, a0
18
19 la a3,handler
20 csrw evec,a3 # set exception handler
21
22 csrr a3,status
23 li a4,(1 << IRQ_COP)
24 slli a4,a4,SR_IM_SHIFT
25 or a3,a3,a4 # enable IM[COP]
26 csrw status,a3
27
28 li a0,33
29 slli a0,a0,6
30 vsetcfg a0
31
32 vtcode2:
33 add x2,x2,x3
34 stop
35
36 handler:
37 vxcptkill
38
39 li TESTNUM,2
40
41 # check cause
42 vxcptcause a3
43 li a4,HWACHA_CAUSE_ILLEGAL_CFG
44 bne a3,a4,fail
45
46 # check vec irq aux
47 vxcptaux a3
48 li a4, 1
49 bne a3,a4,fail
50
51 # make sure vector unit has cleared out
52 vsetcfg 32,0
53 li a3,4
54 vsetvl a3,a3
55
56 la a3,src1
57 la a4,src2
58 vld vx2,a3
59 vld vx3,a4
60 lui a0,%hi(vtcode2)
61 vf %lo(vtcode2)(a0)
62 la a5,dest
63 vsd vx2,a5
64 fence
65
66 ld a1,0(a5)
67 li a2,5
68 li TESTNUM,2
69 bne a1,a2,fail
70 ld a1,8(a5)
71 li TESTNUM,3
72 bne a1,a2,fail
73 ld a1,16(a5)
74 li TESTNUM,4
75 bne a1,a2,fail
76 ld a1,24(a5)
77 li TESTNUM,5
78 bne a1,a2,fail
79
80 TEST_PASSFAIL
81
82 RVTEST_CODE_END
83
84 .data
85 RVTEST_DATA_BEGIN
86
87 TEST_DATA
88
89 src1:
90 .dword 1
91 .dword 2
92 .dword 3
93 .dword 4
94 src2:
95 .dword 4
96 .dword 3
97 .dword 2
98 .dword 1
99 dest:
100 .dword 0xdeadbeefcafebabe
101 .dword 0xdeadbeefcafebabe
102 .dword 0xdeadbeefcafebabe
103 .dword 0xdeadbeefcafebabe
104
105 RVTEST_DATA_END