Add another FP recoding test case
[riscv-tests.git] / isa / rv64sv / illegal_vt_regid.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # xcpt_illegal_vt_regid.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal vt regid trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64SV
14 RVTEST_CODE_BEGIN
15
16 TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2)
17 TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2)
18 TEST_ILLEGAL_VT_REGID(4, 5, 5, add, x1, x2, x7)
19
20 TEST_ILLEGAL_VT_REGID(5, 5, 5, fadd.d, f7, f1, f2)
21 TEST_ILLEGAL_VT_REGID(6, 5, 5, fadd.d, f1, f7, f2)
22 TEST_ILLEGAL_VT_REGID(7, 5, 5, fadd.d, f1, f2, f7)
23
24 TEST_PASSFAIL
25
26 # the handler gets rewritten for every test, but need this for the framework
27 stvec_handler:
28 j fail
29
30 RVTEST_CODE_END
31
32 .data
33 RVTEST_DATA_BEGIN
34
35 TEST_DATA
36
37 src1:
38 .dword 1
39 .dword 2
40 .dword 3
41 .dword 4
42 src2:
43 .dword 4
44 .dword 3
45 .dword 2
46 .dword 1
47 dest:
48 .dword 0xdeadbeefcafebabe
49 .dword 0xdeadbeefcafebabe
50 .dword 0xdeadbeefcafebabe
51 .dword 0xdeadbeefcafebabe
52
53 RVTEST_DATA_END