Merge branch 'master' of github.com:ucb-bar/riscv-tests
[riscv-tests.git] / isa / rv64sv / ma_vld.S
1 #*****************************************************************************
2 # ma_vld.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test misaligned vector ld trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 mfpcr a3,cr0
15 li a4,1
16 slli a5,a4,8
17 or a3,a3,a4 # enable traps
18 mtpcr a3,cr0
19
20 la a3,handler
21 mtpcr a3,cr3 # set exception handler
22
23 vsetcfg 32,0
24 li a3,4
25 vsetvl a3,a3
26
27 la a3, dest+1
28 vld vx2,a3
29 vld vx3,a4
30 lui a0,%hi(vtcode1)
31 vf %lo(vtcode1)(a0)
32 fence
33
34 vtcode1:
35 add x2,x2,x3
36 stop
37
38 vtcode2:
39 add x2,x2,x3
40 stop
41
42 handler:
43 vxcptkill
44
45 li x28,2
46
47 # check cause
48 mfpcr a3,cr6
49 li a4,28
50 bne a3,a4,fail
51
52 # check vec irq aux
53 mfpcr a3,cr2
54 la a4,dest+1
55 bne a3,a4,fail
56
57 # make sure vector unit has cleared out
58 vsetcfg 32,0
59 li a3,4
60 vsetvl a3,a3
61
62 la a3,src1
63 la a4,src2
64 vld vx2,a3
65 vld vx3,a4
66 lui a0,%hi(vtcode2)
67 vf %lo(vtcode2)(a0)
68 la a5,dest
69 vsd vx2,a5
70 fence
71
72 ld a1,0(a5)
73 li a2,5
74 li x28,2
75 bne a1,a2,fail
76 ld a1,8(a5)
77 li x28,3
78 bne a1,a2,fail
79 ld a1,16(a5)
80 li x28,4
81 bne a1,a2,fail
82 ld a1,24(a5)
83 li x28,5
84 bne a1,a2,fail
85
86 TEST_PASSFAIL
87
88 RVTEST_CODE_END
89
90 .data
91 RVTEST_DATA_BEGIN
92
93 TEST_DATA
94
95 src1:
96 .dword 1
97 .dword 2
98 .dword 3
99 .dword 4
100 src2:
101 .dword 4
102 .dword 3
103 .dword 2
104 .dword 1
105 dest:
106 .dword 0xdeadbeefcafebabe
107 .dword 0xdeadbeefcafebabe
108 .dword 0xdeadbeefcafebabe
109 .dword 0xdeadbeefcafebabe
110
111 RVTEST_DATA_END