Add PTE dirty bit test
[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ma_vt_inst.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test misaligned vt instruction trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 li a0, SR_EA | SR_EI
17 csrs status, a0
18
19 la a3,handler
20 csrw evec,a3
21
22 csrr a3,status
23 li a4,(1 << IRQ_COP)
24 slli a4,a4,SR_IM_SHIFT
25 or a3,a3,a4 # enable IM[COP]
26 csrw status,a3
27
28 vsetcfg 32,0
29 li a3,4
30 vsetvl a3,a3
31
32 lui a0,%hi(vtcode1+2)
33 vf %lo(vtcode1+2)(a0)
34 1: j 1b
35
36 vtcode1:
37 add x2,x2,x3
38 stop
39
40 handler:
41 vxcptkill
42
43 li TESTNUM,2
44
45 # check cause
46 vxcptcause a3
47 li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
48 bne a3,a4,fail
49
50 # check badvaddr
51 vxcptaux a3
52 la a4,vtcode1+2
53 andi a3, a3, -4 # mask off lower bits so that may
54 andi a4, a4, -4 # ignore impl. specific behavior
55 bne a3,a4,fail
56
57 # make sure vector unit has cleared out
58 vsetcfg 32,0
59 li a3,4
60 vsetvl a3,a3
61
62 la a3,src1
63 la a4,src2
64 vld vx2,a3
65 vld vx3,a4
66 lui a0,%hi(vtcode1)
67 vf %lo(vtcode1)(a0)
68 la a5,dest
69 vsd vx2,a5
70 fence
71
72 ld a1,0(a5)
73 li a2,5
74 li TESTNUM,2
75 bne a1,a2,fail
76 ld a1,8(a5)
77 li TESTNUM,3
78 bne a1,a2,fail
79 ld a1,16(a5)
80 li TESTNUM,4
81 bne a1,a2,fail
82 ld a1,24(a5)
83 li TESTNUM,5
84 bne a1,a2,fail
85
86 TEST_PASSFAIL
87
88 RVTEST_CODE_END
89
90 .data
91 RVTEST_DATA_BEGIN
92
93 TEST_DATA
94
95 src1:
96 .dword 1
97 .dword 2
98 .dword 3
99 .dword 4
100 src2:
101 .dword 4
102 .dword 3
103 .dword 2
104 .dword 1
105 dest:
106 .dword 0xdeadbeefcafebabe
107 .dword 0xdeadbeefcafebabe
108 .dword 0xdeadbeefcafebabe
109 .dword 0xdeadbeefcafebabe
110
111 RVTEST_DATA_END