add hwacha exception support
[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S
1 #*****************************************************************************
2 # ma_vt_inst.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test misaligned vt instruction trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 setpcr status, SR_EI # enable interrupt
15
16 la a3,handler
17 mtpcr a3,evec # set exception handler
18
19 mfpcr a3,status
20 li a4,(1 << IRQ_COP)
21 slli a4,a4,SR_IM_SHIFT
22 or a3,a3,a4 # enable IM[COP]
23 mtpcr a3,status
24
25 vsetcfg 32,0
26 li a3,4
27 vsetvl a3,a3
28
29 lui a0,%hi(vtcode1+2)
30 vf %lo(vtcode1+2)(a0)
31 1: j 1b
32
33 vtcode1:
34 add x2,x2,x3
35 stop
36
37 handler:
38 vxcptkill
39
40 li x28,2
41
42 # check cause
43 vxcptcause a3
44 li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
45 bne a3,a4,fail
46
47 # check badvaddr
48 vxcptaux a3
49 la a4,vtcode1+2
50 bne a3,a4,fail
51
52 # make sure vector unit has cleared out
53 vsetcfg 32,0
54 li a3,4
55 vsetvl a3,a3
56
57 la a3,src1
58 la a4,src2
59 vld vx2,a3
60 vld vx3,a4
61 lui a0,%hi(vtcode1)
62 vf %lo(vtcode1)(a0)
63 la a5,dest
64 vsd vx2,a5
65 fence
66
67 ld a1,0(a5)
68 li a2,5
69 li x28,2
70 bne a1,a2,fail
71 ld a1,8(a5)
72 li x28,3
73 bne a1,a2,fail
74 ld a1,16(a5)
75 li x28,4
76 bne a1,a2,fail
77 ld a1,24(a5)
78 li x28,5
79 bne a1,a2,fail
80
81 TEST_PASSFAIL
82
83 RVTEST_CODE_END
84
85 .data
86 RVTEST_DATA_BEGIN
87
88 TEST_DATA
89
90 src1:
91 .dword 1
92 .dword 2
93 .dword 3
94 .dword 4
95 src2:
96 .dword 4
97 .dword 3
98 .dword 2
99 .dword 1
100 dest:
101 .dword 0xdeadbeefcafebabe
102 .dword 0xdeadbeefcafebabe
103 .dword 0xdeadbeefcafebabe
104 .dword 0xdeadbeefcafebabe
105
106 RVTEST_DATA_END