1 #*****************************************************************************
3 #-----------------------------------------------------------------------------
5 # Test misaligned vt instruction trap.
8 #include "riscv_test.h"
9 #include "test_macros.h"
14 setpcr status, SR_EA # enable accelerator
15 setpcr status, SR_EI # enable interrupt
18 mtpcr a3,evec # set exception handler
22 slli a4,a4,SR_IM_SHIFT
23 or a3,a3,a4 # enable IM[COP]
45 li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
53 # make sure vector unit has cleared out
102 .dword 0xdeadbeefcafebabe
103 .dword 0xdeadbeefcafebabe
104 .dword 0xdeadbeefcafebabe
105 .dword 0xdeadbeefcafebabe