isa/rv64uv/fma_many.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # fma.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test fma instruction in a vf block.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64UV
  14 RVTEST_CODE_BEGIN
  15
  16   vsetcfg 3,16
  17   li a3,2048
  18   vsetvl a3,a3
  19
  20   la a4,src
  21   fld f0,0(a4)
  22   fld f1,8(a4)
  23   fmv.x.d s0,f0
  24   fmv.x.d s1,f1
  25   vmsv vx1,s0
  26   vmsv vx2,s1
  27   lui a0,%hi(vtcode)
  28   vf %lo(vtcode)(a0)
  29
  30   li a7,0
  31   li a6,400
  32 wait:
  33   addi a7,a7,1
  34   bne a7,a6,wait
  35
  36   fadd.d f0,f0,f1
  37   fmv.x.d s2,f0
  38
  39   la a5,dest
  40   vfsd vf0,a5
  41   fence
  42
  43   la s3,result
  44   ld s4,0(s3)
  45   li TESTNUM,2
  46   bne s2,s4,fail
  47
  48 # verify 1st fadd
  49   li a2,0
  50 loop1:
  51   ld a0,0(a5)
  52   addi TESTNUM,a2,3
  53   bne a0,s4,fail
  54   addi a5,a5,8
  55   addi a2,a2,1
  56   bne a2,a3,loop1
  57
  58 # verify 2nd fmadd
  59   la a5,dest
  60   vfsd vf2,a5
  61   fence
  62   ld s4,8(s3)
  63
  64   li a2,0
  65 loop2:
  66   ld a0,0(a5)
  67   addi TESTNUM,a2,3
  68   bne a0,s4,fail
  69   addi a5,a5,8
  70   addi a2,a2,1
  71   bne a2,a3,loop2
  72
  73 # verify 3rd fmul
  74   la a5,dest
  75   vfsd vf5,a5
  76   fence
  77   ld s4,16(s3)
  78
  79   li a2,0
  80 loop3:
  81   ld a0,0(a5)
  82   addi TESTNUM,a2,3
  83   bne a0,s4,fail
  84   addi a5,a5,8
  85   addi a2,a2,1
  86   bne a2,a3,loop3
  87
  88 # verify 4th fmul
  89   la a5,dest
  90   vfsd vf8,a5
  91   fence
  92   ld s4,24(s3)
  93
  94   li a2,0
  95 loop4:
  96   ld a0,0(a5)
  97   addi TESTNUM,a2,3
  98   bne a0,s4,fail
  99   addi a5,a5,8
 100   addi a2,a2,1
 101   bne a2,a3,loop4
 102
 103 # verify 5th fmadd
 104   la a5,dest
 105   vfsd vf9,a5
 106   fence
 107   ld s4,32(s3)
 108
 109   li a2,0
 110 loop5:
 111   ld a0,0(a5)
 112   addi TESTNUM,a2,3
 113   bne a0,s4,fail
 114   addi a5,a5,8
 115   addi a2,a2,1
 116   bne a2,a3,loop5
 117
 118 # verify 6th fnmadd
 119   la a5,dest
 120   vfsd vf11,a5
 121   fence
 122   ld s4,40(s3)
 123
 124   li a2,0
 125 loop6:
 126   ld a0,0(a5)
 127   addi TESTNUM,a2,3
 128   bne a0,s4,fail
 129   addi a5,a5,8
 130   addi a2,a2,1
 131   bne a2,a3,loop6
 132
 133   j pass
 134
 135 vtcode:
 136   fmv.d.x f0,x1
 137   fmv.d.x f1,x2
 138   fmv.d.x f2,x1
 139   fmv.d.x f3,x2
 140   fmv.d.x f4,x1
 141   fmv.d.x f5,x2
 142   fmv.d.x f6,x1
 143   fmv.d.x f7,x2
 144   fmv.d.x f8,x1
 145   fmv.d.x f9,x2
 146   fmv.d.x f10,x1
 147   fmv.d.x f11,x2
 148   fmv.d.x f12,x1
 149   fmv.d.x f13,x2
 150   fmv.d.x f14,x1
 151   fmv.d.x f15,x2
 152   fadd.d f0,f0,f1
 153   fmadd.d f2,f2,f3,f4
 154   fmul.d f5,f5,f6
 155   fmul.d f8,f5,f7
 156   fmadd.d f9,f9,f10,f9
 157   fnmadd.d f11,f12,f13,f14
 158   stop
 159
 160   TEST_PASSFAIL
 161
 162 RVTEST_CODE_END
 163
 164   .data
 165 RVTEST_DATA_BEGIN
 166
 167   TEST_DATA
 168
 169 src:
 170   .double 1.0
 171   .double 2.0
 172 result:
 173   .double 3.0
 174   .double 3.0
 175   .double 2.0
 176   .double 4.0
 177   .double 4.0
 178   .double -3.0
 179 dest:
 180   .skip 16384
 181
 182 RVTEST_DATA_END