isa/rv64uv/wakeup.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # wakeup.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test wakeup.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64UV
  14 RVTEST_CODE_BEGIN
  15
  16   # make sure these don't choke at the beginning
  17   fence
  18   fence rw,io
  19   fence io,rw
  20
  21   # this shouldn't go through since app vl is zero
  22   la a3,src1
  23   la a4,src2
  24   vld vx2,a3
  25   vld vx3,a4
  26   lui a0,%hi(vtcode1)
  27   vf %lo(vtcode1)(a0)
  28   la a5,dest
  29   vsd vx2,a5
  30   fence
  31
  32   ld a1,0(a5)
  33   li a2,0xdeadbeefcafebabe
  34   li TESTNUM,2
  35   bne a1,a2,fail
  36   ld a1,8(a5)
  37   li TESTNUM,3
  38   bne a1,a2,fail
  39   ld a1,16(a5)
  40   li TESTNUM,4
  41   bne a1,a2,fail
  42   ld a1,24(a5)
  43   li TESTNUM,5
  44   bne a1,a2,fail
  45
  46   # check default hw vector length, which is 32
  47   li a3, 32
  48   vsetvl a3, a3
  49   li a0, 32
  50   li TESTNUM, 6
  51   bne a3, a0, fail
  52
  53   li a3, 33
  54   vsetvl a3, a3
  55   li a0, 32
  56   li TESTNUM, 7
  57   bne a3, a0, fail
  58
  59   li a3, 31
  60   vsetvl a3, a3
  61   li a0, 31
  62   li TESTNUM, 8
  63   bne a3, a0, fail
  64
  65   # now do some vector stuff without vsetcfg
  66   vsetvl x0, x0
  67
  68   li a3, 4
  69   la a4,src1
  70   la a5,src2
  71   vsetvl a3, a3
  72   vld vx2,a4
  73   vld vx3,a5
  74   lui a0,%hi(vtcode1)
  75   vf %lo(vtcode1)(a0)
  76   la a5,dest
  77   vsd vx2,a5
  78   fence
  79
  80   ld a1,0(a5)
  81   li a2,5
  82   li TESTNUM,9
  83   bne a1,a2,fail
  84   ld a1,8(a5)
  85   li TESTNUM,10
  86   bne a1,a2,fail
  87   ld a1,16(a5)
  88   li TESTNUM,11
  89   bne a1,a2,fail
  90   ld a1,24(a5)
  91   li TESTNUM,12
  92   bne a1,a2,fail
  93
  94   # initialize dest memory
  95   li a3, 0xdeadbeefcafebabe
  96   sd a3, 0(a5)
  97   sd a3, 8(a5)
  98   sd a3, 16(a5)
  99   sd a3, 24(a5)
 100
 101   # test app vl zero again
 102   li a3, 0
 103   vsetvl a3, a3
 104
 105   la a3,src1
 106   la a4,src2
 107   vld vx2,a3
 108   vld vx3,a4
 109   lui a0,%hi(vtcode1)
 110   vf %lo(vtcode1)(a0)
 111   la a5,dest
 112   vsd vx2,a5
 113   fence
 114
 115   ld a1,0(a5)
 116   li a2,0xdeadbeefcafebabe
 117   li TESTNUM,13
 118   bne a1,a2,fail
 119   ld a1,8(a5)
 120   li TESTNUM,14
 121   bne a1,a2,fail
 122   ld a1,16(a5)
 123   li TESTNUM,15
 124   bne a1,a2,fail
 125   ld a1,24(a5)
 126   li TESTNUM,16
 127   bne a1,a2,fail
 128
 129   j pass
 130
 131 vtcode1:
 132   add x2,x2,x3
 133   stop
 134
 135   TEST_PASSFAIL
 136
 137 RVTEST_CODE_END
 138
 139   .data
 140 RVTEST_DATA_BEGIN
 141
 142   TEST_DATA
 143
 144 src1:
 145   .dword 1
 146   .dword 2
 147   .dword 3
 148   .dword 4
 149 src2:
 150   .dword 4
 151   .dword 3
 152   .dword 2
 153   .dword 1
 154 dest:
 155   .dword 0xdeadbeefcafebabe
 156   .dword 0xdeadbeefcafebabe
 157   .dword 0xdeadbeefcafebabe
 158   .dword 0xdeadbeefcafebabe
 159
 160 RVTEST_DATA_END