isa/rv64uv/wakeup.S

   1 #*****************************************************************************
   2 # wakeup.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test wakeup.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64U
  12 RVTEST_CODE_BEGIN
  13
  14   # make sure these don't choke at the beginning
  15   fence.v.l
  16   fence.v.l
  17   fence.v.g
  18   fence.v.g
  19
  20   # this shouldn't go through since app vl is zero
  21   la a3,src1
  22   la a4,src2
  23   vld vx2,a3
  24   vld vx3,a4
  25   lui a0,%hi(vtcode1)
  26   vf %lo(vtcode1)(a0)
  27   la a5,dest
  28   vsd vx2,a5
  29   fence.v.l
  30
  31   ld a1,0(a5)
  32   li a2,0xdeadbeefcafebabe
  33   li x28,2
  34   bne a1,a2,fail
  35   ld a1,8(a5)
  36   li x28,3
  37   bne a1,a2,fail
  38   ld a1,16(a5)
  39   li x28,4
  40   bne a1,a2,fail
  41   ld a1,24(a5)
  42   li x28,5
  43   bne a1,a2,fail
  44
  45   # check default hw vector length, which is 32
  46   li a3, 32
  47   vsetvl a3, a3
  48   li a0, 32
  49   li x28, 6
  50   bne a3, a0, fail
  51
  52   li a3, 33
  53   vsetvl a3, a3
  54   li a0, 32
  55   li x28, 7
  56   bne a3, a0, fail
  57
  58   li a3, 31
  59   vsetvl a3, a3
  60   li a0, 31
  61   li x28, 8
  62   bne a3, a0, fail
  63
  64   # now do some vector stuff without vvcfgivl
  65   vsetvl x0, x0
  66
  67   li a3, 4
  68   la a4,src1
  69   la a5,src2
  70   vsetvl a3, a3
  71   vld vx2,a4
  72   vld vx3,a5
  73   lui a0,%hi(vtcode1)
  74   vf %lo(vtcode1)(a0)
  75   la a5,dest
  76   vsd vx2,a5
  77   fence.v.l
  78
  79   ld a1,0(a5)
  80   li a2,5
  81   li x28,9
  82   bne a1,a2,fail
  83   ld a1,8(a5)
  84   li x28,10
  85   bne a1,a2,fail
  86   ld a1,16(a5)
  87   li x28,11
  88   bne a1,a2,fail
  89   ld a1,24(a5)
  90   li x28,12
  91   bne a1,a2,fail
  92
  93   # initialize dest memory
  94   li a3, 0xdeadbeefcafebabe
  95   sd a3, 0(a5)
  96   sd a3, 8(a5)
  97   sd a3, 16(a5)
  98   sd a3, 24(a5)
  99
 100   # test app vl zero again
 101   li a3, 0
 102   vsetvl a3, a3
 103
 104   la a3,src1
 105   la a4,src2
 106   vld vx2,a3
 107   vld vx3,a4
 108   lui a0,%hi(vtcode1)
 109   vf %lo(vtcode1)(a0)
 110   la a5,dest
 111   vsd vx2,a5
 112   fence.v.l
 113
 114   ld a1,0(a5)
 115   li a2,0xdeadbeefcafebabe
 116   li x28,13
 117   bne a1,a2,fail
 118   ld a1,8(a5)
 119   li x28,14
 120   bne a1,a2,fail
 121   ld a1,16(a5)
 122   li x28,15
 123   bne a1,a2,fail
 124   ld a1,24(a5)
 125   li x28,16
 126   bne a1,a2,fail
 127
 128   j pass
 129
 130 vtcode1:
 131   add x2,x2,x3
 132   stop
 133
 134   TEST_PASSFAIL
 135
 136 RVTEST_CODE_END
 137
 138   .data
 139 RVTEST_DATA_BEGIN
 140
 141   TEST_DATA
 142
 143 src1:
 144   .dword 1
 145   .dword 2
 146   .dword 3
 147   .dword 4
 148 src2:
 149   .dword 4
 150   .dword 3
 151   .dword 2
 152   .dword 1
 153 dest:
 154   .dword 0xdeadbeefcafebabe
 155   .dword 0xdeadbeefcafebabe
 156   .dword 0xdeadbeefcafebabe
 157   .dword 0xdeadbeefcafebabe
 158
 159 RVTEST_DATA_END