correctly set SR_EA bit for all vector physical tests

[riscv-tests.git] / env / v / riscv_test.h

diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h
index d9b23fb60e4d1f3b0782257351aeb25d7ad6a893..20d06900cf9ec244fea52e7226296dedba840faa 100644 (file)
--- a/env/v/riscv_test.h
+++ b/env/v/riscv_test.h
@@ -12,9 +12,10 @@
 #define RVTEST_RV64UF                                                   \
   .macro init;                                                          \
   fssr x0;                                                              \
-  .endm 
+  .endm
 
-#define RVTEST_VEC_ENABLE                                               \
+#define RVTEST_RV64UV                                                   \
+       RVTEST_RV64UF
 
 #define RVTEST_CODE_BEGIN                                               \
         .text;                                                          \