Enable LR/SC tests, even for uniprocessors

[riscv-tests.git] / isa / rv64ui / lrsc.S

diff --git a/isa/rv64ui/lrsc.S b/isa/rv64ui/lrsc.S
index 6c4904efa79846337384db58e89a4349cc5faf33..9422739c6c5b6768617ad93459434916c1c22148 100644 (file)
--- a/isa/rv64ui/lrsc.S
+++ b/isa/rv64ui/lrsc.S
@@ -32,6 +32,7 @@ TEST_CASE( 2, a4, 1, \
 )
 
 # make sure that sc with the wrong reservation fails.
+# TODO is this actually mandatory behavior?
 TEST_CASE( 3, a4, 1, \
   la a0, foo; \
   add a1, a0, 1024; \