correctly set SR_EA bit for all vector physical tests

[riscv-tests.git] / isa / rv64uv / amoadd_d.S

diff --git a/isa/rv64uv/amoadd_d.S b/isa/rv64uv/amoadd_d.S
index ce3c6a6635364f1e6ef8e13f3b1047dca0acbe2c..68b0ba15843873f2e8c3af8d74e645c51784a4b8 100644 (file)
--- a/isa/rv64uv/amoadd_d.S
+++ b/isa/rv64uv/amoadd_d.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0