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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git]
/
isa
/
rv64uv
/
fmovn.S
diff --git
a/isa/rv64uv/fmovn.S
b/isa/rv64uv/fmovn.S
index a943326c5086eff00a4001993f3c70db4c4c12b2..47a6a3936d5e20ed291d89e91c81177ae16ed5bf 100644
(file)
--- a/
isa/rv64uv/fmovn.S
+++ b/
isa/rv64uv/fmovn.S
@@
-8,7
+8,7
@@
#include "riscv_test.h"
#include "test_macros.h"
-RVTEST_RV64U
+RVTEST_RV64U
V
RVTEST_CODE_BEGIN
vsetcfg 4,2