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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / vsetcfg.S
diff --git a/isa/rv64uv/vsetcfg.S b/isa/rv64uv/vsetcfg.S
index 896278297900c5b13af11c12b7c228055cfd7b08..f0f532e601dee9da4d39fef70cdfcea072bf24c2 100644 (file)
--- a/isa/rv64uv/vsetcfg.S
+++ b/isa/rv64uv/vsetcfg.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   #-------------------------------------------------------------