git.libre-soc.org Git - riscv-tests.git/history

2018-08-17	Srivatsa Yogendra	making mtvec_handler global (#150)	commit \| commitdiff
2017-05-18	Megan Wachs	Merge pull request #52 from riscv/vcs_sim_cmd	commit \| commitdiff
2017-05-17	Andrew Waterman	Manually assemble bad shift amount, since assembler...	commit \| commitdiff
2016-03-15	Andrew Waterman	Merge branch 'priv-1.9'	commit \| commitdiff
2016-03-03	Andrew Waterman	Some S-mode tests really only belong in M-mode	commit \| commitdiff