src/main/scala/devices/pwm/PWMPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import config._
   6 import diplomacy.LazyModule
   7 import rocketchip.{TopNetwork,TopNetworkModule}
   8 import uncore.tilelink2.TLFragmenter
   9
  10 import sifive.blocks.devices.gpio._
  11
  12 class PWMPortIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
  13   val port = Vec(c.ncmp, Bool()).asOutput
  14   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
  15 }
  16
  17 class PWMPinsIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
  18   val pwm = Vec(c.ncmp, new GPIOPin)
  19 }
  20
  21 class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
  22   val io = new Bundle {
  23     val pwm = new PWMPortIO(c).flip()
  24     val pins = new PWMPinsIO(c)
  25   }
  26
  27   GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
  28 }
  29
  30 trait PeripheryPWM {
  31   this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
  32
  33   val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) =>
  34     val pwm = LazyModule(new TLPWM(c) { override lazy val  valName = Some(s"pwm$i") })
  35     pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
  36     intBus.intnode := pwm.intnode
  37     pwm
  38   }
  39 }
  40
  41 trait PeripheryPWMBundle {
  42   this: {
  43     val p: Parameters
  44     val pwmConfigs: Seq[PWMConfig]
  45   } =>
  46   val pwm_bc = pwmConfigs.map(_.bc).reduce(_.union(_))
  47   val pwms = Vec(pwmConfigs.size, new PWMPortIO(pwm_bc)(p))
  48 }
  49
  50 trait PeripheryPWMModule {
  51   this: TopNetworkModule {
  52     val outer: PeripheryPWM
  53     val io: PeripheryPWMBundle
  54   } =>
  55   (io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) =>
  56     io.port := device.module.io.gpio
  57   }
  58 }