src/main/scala/ip/xilinx/vc707mig/vc707mig.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.ip.xilinx.vc707mig
   3
   4 import Chisel._
   5 import config._
   6 import junctions._
   7
   8 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
   9 // Black Box
  10 // Signals named _exactly_ as per MIG generated verilog
  11
  12 trait VC707MIGUnidirectionalIODDR extends Bundle {
  13   //outputs
  14   val ddr3_addr             = Bits(OUTPUT,14)
  15   val ddr3_ba               = Bits(OUTPUT,3)
  16   val ddr3_ras_n            = Bool(OUTPUT)
  17   val ddr3_cas_n            = Bool(OUTPUT)
  18   val ddr3_we_n             = Bool(OUTPUT)
  19   val ddr3_reset_n          = Bool(OUTPUT)
  20   val ddr3_ck_p             = Bits(OUTPUT,1)
  21   val ddr3_ck_n             = Bits(OUTPUT,1)
  22   val ddr3_cke              = Bits(OUTPUT,1)
  23   val ddr3_cs_n             = Bits(OUTPUT,1)
  24   val ddr3_dm               = Bits(OUTPUT,8)
  25   val ddr3_odt              = Bits(OUTPUT,1)
  26 }
  27
  28 //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
  29 trait VC707MIGUnidirectionalIOClocksReset extends Bundle {
  30   //inputs
  31   //differential system clocks
  32   val sys_clk_n             = Bool(INPUT)
  33   val sys_clk_p             = Bool(INPUT)
  34   //user interface signals
  35   val ui_clk                = Clock(OUTPUT)
  36   val ui_clk_sync_rst       = Bool(OUTPUT)
  37   val mmcm_locked           = Bool(OUTPUT)
  38   val aresetn               = Bool(INPUT)
  39   //misc
  40   val init_calib_complete   = Bool(OUTPUT)
  41   val sys_rst               = Bool(INPUT)
  42 }
  43
  44 //scalastyle:off
  45 //turn off linter: blackbox name must match verilog module
  46 class vc707mig(implicit val p:Parameters) extends BlackBox
  47 {
  48   val io = new Bundle with VC707MIGUnidirectionalIODDR
  49                       with VC707MIGUnidirectionalIOClocksReset {
  50     // bidirectional signals on blackbox interface
  51     // defined here as an output so "__inout" signal name does not have to be used
  52     // verilog does not check the
  53     val ddr3_dq               = Bits(OUTPUT,64)
  54     val ddr3_dqs_n            = Bits(OUTPUT,8)
  55     val ddr3_dqs_p            = Bits(OUTPUT,8)
  56     // User interface signals
  57     val app_sr_req            = Bool(INPUT)
  58     val app_ref_req           = Bool(INPUT)
  59     val app_zq_req            = Bool(INPUT)
  60     val app_sr_active         = Bool(OUTPUT)
  61     val app_ref_ack           = Bool(OUTPUT)
  62     val app_zq_ack            = Bool(OUTPUT)
  63     //axi_s
  64     //slave interface write address ports
  65     val s_axi_awid            = Bits(INPUT,4)
  66     val s_axi_awaddr          = Bits(INPUT,30)
  67     val s_axi_awlen           = Bits(INPUT,8)
  68     val s_axi_awsize          = Bits(INPUT,3)
  69     val s_axi_awburst         = Bits(INPUT,2)
  70     val s_axi_awlock          = Bits(INPUT,1)
  71     val s_axi_awcache         = Bits(INPUT,4)
  72     val s_axi_awprot          = Bits(INPUT,3)
  73     val s_axi_awqos           = Bits(INPUT,4)
  74     val s_axi_awvalid         = Bool(INPUT)
  75     val s_axi_awready         = Bool(OUTPUT)
  76     //slave interface write data ports
  77     val s_axi_wdata           = Bits(INPUT,64)
  78     val s_axi_wstrb           = Bits(INPUT,8)
  79     val s_axi_wlast           = Bool(INPUT)
  80     val s_axi_wvalid          = Bool(INPUT)
  81     val s_axi_wready          = Bool(OUTPUT)
  82     //slave interface write response ports
  83     val s_axi_bready          = Bool(INPUT)
  84     val s_axi_bid             = Bits(OUTPUT,4)
  85     val s_axi_bresp           = Bits(OUTPUT,2)
  86     val s_axi_bvalid          = Bool(OUTPUT)
  87     //slave interface read address ports
  88     val s_axi_arid            = Bits(INPUT,4)
  89     val s_axi_araddr          = Bits(INPUT,30)
  90     val s_axi_arlen           = Bits(INPUT,8)
  91     val s_axi_arsize          = Bits(INPUT,3)
  92     val s_axi_arburst         = Bits(INPUT,2)
  93     val s_axi_arlock          = Bits(INPUT,1)
  94     val s_axi_arcache         = Bits(INPUT,4)
  95     val s_axi_arprot          = Bits(INPUT,3)
  96     val s_axi_arqos           = Bits(INPUT,4)
  97     val s_axi_arvalid         = Bool(INPUT)
  98     val s_axi_arready         = Bool(OUTPUT)
  99     //slave interface read data ports
 100     val s_axi_rready          = Bool(INPUT)
 101     val s_axi_rid             = Bits(OUTPUT,4)
 102     val s_axi_rdata           = Bits(OUTPUT,64)
 103     val s_axi_rresp           = Bits(OUTPUT,2)
 104     val s_axi_rlast           = Bool(OUTPUT)
 105     val s_axi_rvalid          = Bool(OUTPUT)
 106     //misc
 107     val device_temp           = Bits(OUTPUT,12)
 108   }
 109 }
 110 //scalastyle:on