ls180/SPBlock_512W64B8W.v

   1 // SPBlock_512W64B8W simulation mode
   2 module SPBlock_512W64B8W(
   3     input clk,
   4     input [8:0] a,
   5     input [63:0] d,
   6     output [63:0] q,
   7     // Width of WE determines the write granularity
   8     input [7:0] we
   9 );
  10
  11 genvar i;
  12
  13 reg [63:0] ram [511:0];
  14 wire[7:0] d_split [7:0];
  15 reg [8:0] a_hold;
  16
  17 always @(posedge clk) begin
  18     a_hold <= a;
  19 end
  20
  21 assign q = ram[a_hold];
  22
  23 generate
  24     for (i = 0; i < 8; i = i + 1) begin
  25         assign d_split[i] = d[((i + 1)*8 - 1):i*8];
  26
  27         always @(posedge clk) begin
  28             if (we[i]) begin
  29                 ram[a][((i + 1)*8 - 1):i*8] = d_split[i];
  30             end
  31         end
  32     end
  33 endgenerate
  34
  35 endmodule