fix iovdd/iovss in-to-std_logic conversion
[soc-cocotb-sim.git] / ls180 /
2021-04-17 Luke Kenneth Casso... fix iovdd/iovss in-to-std_logic conversion
2021-04-16 Luke Kenneth Casso... get pre-coriolis2 verilator (wishbone) functional
2021-04-16 Luke Kenneth Casso... upload 32-bit wishbone data not 64-bit test data
2021-04-16 Luke Kenneth Casso... corrections to wishbone test
2021-04-16 Luke Kenneth Casso... corrections to wishbone test
2021-04-14 Luke Kenneth Casso... add test boundary scan hard-coded test
2021-04-14 Luke Kenneth Casso... try chip_r adder test (works)
2021-04-14 Luke Kenneth Casso... remove async, use yield
2021-04-13 Luke Kenneth Casso... get jtag tests running on basic adder
2021-04-13 Luke Kenneth Casso... convert wb test to async
2021-04-13 Luke Kenneth Casso... resolving pin names (to litex ls180)
2021-04-13 Luke Kenneth Casso... more post-processing of vst files
2021-04-12 Luke Kenneth Casso... more vst corrections, for chip definition
2021-04-11 Luke Kenneth Casso... sorting out cts (post p&r)
2021-04-10 Luke Kenneth Casso... adding edited versions of chip/corona
2021-04-10 Luke Kenneth Casso... use vcd for wave output not ghw
2021-04-10 Luke Kenneth Casso... sigh, no wrap - use direct
2021-04-10 Luke Kenneth Casso... add ghdl wishbone basic test
2021-04-07 Luke Kenneth Casso... correct iverilog script errors
2021-04-07 Luke Kenneth Casso... add verilator cocotb runner
2021-04-06 Luke Kenneth Casso... remove wb test from test.py
2021-04-06 Luke Kenneth Casso... add test wishbone (separate from test.py)
2021-04-06 Staf VerhaegenFunction is a generator.
2021-04-06 Staf VerhaegenFix pre-layout simulation with 4K SRAM blocks.
2021-04-06 Staf VerhaegenAdd sim models for SRAM block.
2021-04-06 Luke Kenneth Casso... add wishbone sim gtk test script
2021-04-06 Luke Kenneth Casso... add comments
2021-04-06 Luke Kenneth Casso... fix wishbone jtag test to run: results not correct yet
2021-04-06 Luke Kenneth Casso... add first cut at wishbone jtag unit test
2021-04-06 Luke Kenneth Casso... whitespace
2021-04-04 Luke Kenneth Casso... 80 char linewrap
2021-04-04 Staf VerhaegenTest different combinations of i, o, oe for InTriOut
2021-04-03 Staf VerhaegenSupport running tb on test_issuer subblock.
2021-04-03 Staf VerhaegenUpdate gitignore.
2021-04-02 Staf VerhaegenFull boundary scan.
2021-04-02 Staf VerhaegenTypo.
2021-04-02 Staf VerhaegenAdd helper class JTAGPin
2021-04-02 Staf VerhaegenFirst version of boundary scan test bench.
2021-04-02 Staf Verhaegenpre_pnr/test.py: Fix idcode SVF test name.
2021-04-02 Staf Verhaegenpre_pnr/test.py: Reset JTAG before executing SVF.
2021-04-01 Luke Kenneth Casso... TWI enabled in boundary scan
2021-04-01 Luke Kenneth Casso... show how to get the boundary scan information from...
2021-04-01 Luke Kenneth Casso... add one more up to path
2021-04-01 Luke Kenneth Casso... move pre_pnr cocotb sim to soc-cocotb-sim directory
2021-04-01 Luke Kenneth Casso... move post-pnr to new subdirectory
2021-04-01 Luke Kenneth Casso... update README
2021-04-01 Luke Kenneth Casso... sort out Makefile for building
2021-04-01 Luke Kenneth Casso... ha! got IDCODE and reset test to work
2021-04-01 Luke Kenneth Casso... match ir_width with experiment10 and do not overwrite...
2021-04-01 Luke Kenneth Casso... connect up jtag corona pads
2021-04-01 Luke Kenneth Casso... add cocotb testbench
2021-04-01 Luke Kenneth Casso... remove not-needed thing from cocotb Makefile
2021-04-01 Luke Kenneth Casso... add first cocotb Makefile
2021-04-01 Luke Kenneth Casso... add "make corona" option
2021-04-01 Luke Kenneth Casso... compile all libraries, use --std=08 it passes
2021-04-01 Luke Kenneth Casso... add vst corrections program
2021-04-01 Luke Kenneth Casso... do niolib conversion as well as nsxlib
2021-03-31 Luke Kenneth Casso... build vhd objects
2021-03-31 Luke Kenneth Casso... add conversion from alliance vbe to vst using coriolis2...
2021-03-31 Luke Kenneth Casso... start on Makefile, add notes, add alliance-check-toolki...
2021-03-29 Luke Kenneth Casso... add initial empty README.txt in ls180 directory