TLB/test/test_cam.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from Cam import Cam
   8
   9 from test_helper import assert_eq, assert_ne
  10
  11 def set_cam(dut, e, we, a, d):
  12     yield dut.enable.eq(e)
  13     yield dut.write_enable.eq(we)
  14     yield dut.address_in.eq(a)
  15     yield dut.data_in.eq(d)
  16     yield
  17
  18 def check_single_match(dut, dh, op):
  19     out_sm = yield dut.single_match
  20     if op == 0:
  21         assert_eq("Single Match", out_sm, dh)
  22     else:
  23         assert_ne("Single Match", out_sm, dh)
  24
  25 def check_match_address(dut, ma, op):
  26     out_ma = yield dut.match_address
  27     if op == 0:
  28         assert_eq("Match Address", out_ma, ma)
  29     else:
  30         assert_ne("Match Address", out_ma, ma)
  31
  32 def check_all(dut, single_match, match_address, sm_op, ma_op):
  33     yield from check_single_match(dut, single_match, sm_op)
  34     yield from check_match_address(dut, match_address, ma_op)
  35
  36
  37 def testbench(dut):
  38     # NA
  39     enable = 1
  40     write_enable = 0
  41     address = 0
  42     data = 0
  43     single_match = 0
  44     yield from set_cam(dut, enable, write_enable, address, data)
  45     yield from check_single_match(dut, single_match, 0)
  46
  47     # Read Miss
  48     # Note that the default starting entry data bits are all 0
  49     enable = 1
  50     write_enable = 0
  51     address = 0
  52     data = 1
  53     single_match = 0
  54     yield from set_cam(dut, enable, write_enable, address, data)
  55     yield
  56     yield from check_single_match(dut, single_match, 0)
  57
  58     # Write Entry 0
  59     enable = 1
  60     write_enable = 1
  61     address = 0
  62     data = 4
  63     single_match = 0
  64     yield from set_cam(dut, enable, write_enable, address, data)
  65     yield
  66     yield from check_single_match(dut, single_match, 0)
  67
  68     # Read Hit Entry 0
  69     enable = 1
  70     write_enable = 0
  71     address = 0
  72     data = 4
  73     single_match = 1
  74     yield from set_cam(dut, enable, write_enable, address, data)
  75     yield
  76     yield from check_all(dut, single_match, address, 0, 0)
  77
  78     # Search Hit
  79     enable = 1
  80     write_enable = 0
  81     address = 0
  82     data = 4
  83     single_match = 1
  84     yield from set_cam(dut, enable, write_enable, address, data)
  85     yield
  86     yield from check_all(dut, single_match, address, 0, 0)
  87
  88     # Search Miss
  89     enable = 1
  90     write_enable = 0
  91     address = 0
  92     data = 5
  93     single_match = 0
  94     yield from set_cam(dut, enable, write_enable, address, data)
  95     yield
  96     yield from check_single_match(dut, single_match, 0)
  97
  98     yield
  99
 100
 101 if __name__ == "__main__":
 102     dut = Cam(4, 4)
 103     run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_test.vcd")
 104     print("Cam Unit Test Success")