TLB/test/test_cam_entry.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from test_helper import assert_eq, assert_ne
   8 from CamEntry import CamEntry
   9
  10 # This function allows for the easy setting of values to the Cam Entry
  11 # unless the key is incorrect
  12 # Arguments:
  13 #   dut: The CamEntry being tested
  14 #   c (command): NA (0), Read (1), Write (2), Reserve (3)
  15 #   d (data): The data to be set
  16 def set_cam_entry(dut, c, d):
  17     # Write desired values
  18     yield dut.command.eq(c)
  19     yield dut.data_in.eq(d)
  20     yield
  21     # Reset all lines
  22     yield dut.command.eq(0)
  23     yield dut.data_in.eq(0)
  24     yield
  25
  26 # Checks the data state of the CAM entry
  27 # Arguments:
  28 #   dut: The CamEntry being tested
  29 #   d (Data): The expected data
  30 #   op (Operation): (0 => ==), (1 => !=)
  31 def check_data(dut, d, op):
  32     out_d = yield dut.data
  33     if op == 0:
  34         assert_eq("Data", out_d, d)
  35     else:
  36         assert_ne("Data", out_d, d)
  37
  38 # Checks the match state of the CAM entry
  39 # Arguments:
  40 #   dut: The CamEntry being tested
  41 #   m (Match): The expected match
  42 #   op (Operation): (0 => ==), (1 => !=)
  43 def check_match(dut, m, op):
  44     out_m = yield dut.match
  45     if op == 0:
  46         assert_eq("Match", out_m, m)
  47     else:
  48         assert_ne("Match", out_m, m)
  49
  50 # Checks the state of the CAM entry
  51 # Arguments:
  52 #   dut: The CamEntry being tested
  53 #   d (data): The expected data
  54 #   m (match): The expected match
  55 #   d_op (Operation): The operation for the data assertion (0 => ==), (1 => !=)
  56 #   m_op (Operation): The operation for the match assertion (0 => ==), (1 => !=)
  57 def check_all(dut, d, m, d_op, m_op):
  58     yield from check_data(dut, d, d_op)
  59     yield from check_match(dut, m, m_op)
  60
  61 # This testbench goes through the paces of testing the CamEntry module
  62 # It is done by writing and then reading various combinations of key/data pairs
  63 # and reading the results with varying keys to verify the resulting stored
  64 # data is correct.
  65 def testbench(dut):
  66     # Check write
  67     command = 2
  68     data = 1
  69     match = 0
  70     yield from set_cam_entry(dut, command, data)
  71     yield from check_all(dut, data, match, 0, 0)
  72
  73     # Check read miss
  74     command = 1
  75     data = 2
  76     match = 0
  77     yield from set_cam_entry(dut, command, data)
  78     yield from check_all(dut, data, match, 1, 0)
  79
  80     # Check read hit
  81     command = 1
  82     data = 1
  83     match = 1
  84     yield from set_cam_entry(dut, command, data)
  85     yield from check_all(dut, data, match, 0, 0)
  86
  87     # Check overwrite
  88     command = 2
  89     data = 5
  90     match = 0
  91     yield from set_cam_entry(dut, command, data)
  92     yield
  93     yield from check_all(dut, data, match, 0, 0)
  94
  95     # Check read hit
  96     command = 1
  97     data = 5
  98     match = 1
  99     yield from set_cam_entry(dut, command, data)
 100     yield from check_all(dut, data, match, 0, 0)
 101
 102     # Check reset
 103     command = 3
 104     data = 0
 105     match = 0
 106     yield from set_cam_entry(dut, command, data)
 107     yield from check_all(dut, data, match, 0, 0)
 108
 109     # Extra clock cycle for waveform
 110     yield
 111
 112 if __name__ == "__main__":
 113     dut = CamEntry(4)
 114     run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_entry_test.vcd")
 115     print("CamEntry Unit Test Success")