src/soc/branch/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.decoder.power_decoder2 import Data
   4
   5
   6 class IntegerData:
   7
   8     def __init__(self, pspec):
   9         self.ctx = FPPipeContext(pspec)
  10         self.muxid = self.ctx.muxid
  11
  12     def __iter__(self):
  13         yield from self.ctx
  14
  15     def eq(self, i):
  16         return [self.ctx.eq(i.ctx)]
  17
  18
  19 class BranchInputData(IntegerData):
  20     def __init__(self, pspec):
  21         super().__init__(pspec)
  22         # We need both lr and spr for bclr and bcctrl. Bclr can read
  23         # from both ctr and lr, and bcctrl can write to both ctr and
  24         # lr.
  25         self.lr = Signal(64, reset_less=True)
  26         self.spr = Signal(64, reset_less=True)
  27         self.cr = Signal(32, reset_less=True)
  28         self.nia = Signal(64, reset_less=True)
  29
  30     def __iter__(self):
  31         yield from super().__iter__()
  32         yield self.lr
  33         yield self.spr
  34         yield self.cr
  35         yield self.nia
  36
  37     def eq(self, i):
  38         lst = super().eq(i)
  39         return lst + [self.lr.eq(i.lr), self.spr.eq(i.lr),
  40                       self.cr.eq(i.cr), self.nia.eq(i.nia)]
  41
  42
  43 class BranchOutputData(IntegerData):
  44     def __init__(self, pspec):
  45         super().__init__(pspec)
  46         self.lr = Data(64, name="lr")
  47         self.spr = Data(64, name="spr")
  48         self.nia_out = Data(64, name="nia_out")
  49
  50     def __iter__(self):
  51         yield from super().__iter__()
  52         yield from self.lr
  53         yield from self.spr
  54         yield from self.nia_out
  55
  56     def eq(self, i):
  57         lst = super().eq(i)
  58         return lst + [self.lr.eq(i.lr), self.spr.eq(i.spr),
  59                       self.nia_out.eq(i.nia_out)]