351d09cc849a8df754ec7cdfb9521f15bb27ea91
3 This first version is intended for prototyping and test purposes:
4 it has "direct" access to Memory.
6 The intention is that this version remains an integral part of the
7 test infrastructure, and, just as with minerva's memory arrangement,
8 a dynamic runtime config *selects* alternative memory arrangements
9 rather than *replaces and discards* this code.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
18 from nmigen
.compat
.sim
import run_simulation
19 from nmigen
.cli
import verilog
, rtlil
20 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Array
, Cat
21 from nmutil
.iocontrol
import RecordObject
22 from nmigen
.utils
import log2_int
23 from nmigen
.hdl
.rec
import Record
, Layout
25 from nmutil
.latch
import SRLatch
, latchregister
26 from soc
.decoder
.power_decoder2
import Data
27 from soc
.decoder
.power_enums
import InternalOp
28 from soc
.regfile
.regfile
import ortreereduce
29 from nmutil
.util
import treereduce
31 from soc
.experiment
.compldst
import CompLDSTOpSubset
32 from soc
.decoder
.power_decoder2
import Data
33 #from nmutil.picker import PriorityPicker
34 from nmigen
.lib
.coding
import PriorityEncoder
36 # for testing purposes
37 from soc
.experiment
.testmem
import TestMemory
39 class PortInterface(RecordObject
):
42 defines the interface - the API - that the LDSTCompUnit connects
43 to. note that this is NOT a "fire-and-forget" interface. the
44 LDSTCompUnit *must* be kept appraised that the request is in
45 progress, and only when it has a 100% successful completion rate
46 can the notification be given (busy dropped).
48 The interface FSM rules are as follows:
50 * if busy_o is asserted, a LD/ST is in progress. further
51 requests may not be made until busy_o is deasserted.
53 * only one of is_ld_i or is_st_i may be asserted. busy_o
54 will immediately be asserted and remain asserted.
56 * addr.ok is to be asserted when the LD/ST address is known.
57 addr.data is to be valid on the same cycle.
59 addr.ok and addr.data must REMAIN asserted until busy_o
60 is de-asserted. this ensures that there is no need
61 for the L0 Cache/Buffer to have an additional address latch
62 (because the LDSTCompUnit already has it)
64 * addr_ok_o (or addr_exc_o) must be waited for. these will
65 be asserted *only* for one cycle and one cycle only.
67 * addr_exc_o will be asserted if there is no chance that the
68 memory request may be fulfilled.
70 busy_o is deasserted on the same cycle as addr_exc_o is asserted.
72 * conversely: addr_ok_o must *ONLY* be asserted if there is a
73 HUNDRED PERCENT guarantee that the memory request will be
76 * for a LD, ld.ok will be asserted - for only one clock cycle -
77 at any point in the future that is acceptable to the underlying
78 Memory subsystem. the recipient MUST latch ld.data on that cycle.
80 busy_o is deasserted on the same cycle as ld.ok is asserted.
82 * for a ST, st.ok may be asserted only after addr_ok_o had been
83 asserted, alongside valid st.data at the same time. st.ok
84 must only be asserted for one cycle.
86 the underlying Memory is REQUIRED to pick up that data and
87 guarantee its delivery. no back-acknowledgement is required.
89 busy_o is deasserted on the cycle AFTER st.ok is asserted.
92 def __init__(self
, name
=None, regwid
=64, addrwid
=48):
95 self
._addrwid
= addrwid
97 RecordObject
.__init
__(self
, name
=name
)
99 # distinguish op type (ld/st)
100 self
.is_ld_i
= Signal(reset_less
=True)
101 self
.is_st_i
= Signal(reset_less
=True)
102 self
.op
= CompLDSTOpSubset() # hm insn_type ld/st duplicates here
105 self
.busy_o
= Signal(reset_less
=True) # do not use if busy
106 self
.go_die_i
= Signal(reset_less
=True) # back to reset
107 self
.addr
= Data(addrwid
, "addr_i") # addr/addr-ok
108 # addr is valid (TLB, L1 etc.)
109 self
.addr_ok_o
= Signal(reset_less
=True)
110 self
.addr_exc_o
= Signal(reset_less
=True) # TODO, "type" of exception
113 self
.ld
= Data(regwid
, "ld_data_o") # ok to be set by L0 Cache/Buf
114 self
.st
= Data(regwid
, "st_data_i") # ok to be set by CompUnit
119 class DualPortSplitter(Elaboratable
):
122 * one incoming PortInterface
123 * two *OUTGOING* PortInterfaces
124 * uses LDSTSplitter to do it
126 (actually, thinking about it LDSTSplitter could simply be
127 modified to conform to PortInterface: one in, two out)
129 once that is done each pair of ports may be wired directly
130 to the dual ports of L0CacheBuffer
135 class DataMergerRecord(Record
):
137 {data: 128 bit, byte_enable: 16 bit}
140 def __init__(self
, name
=None):
141 layout
= (('data', 128),
145 Record
.__init
__(self
, Layout(layout
), name
=name
)
147 #FIXME: make resetless
151 class DataMerger(Elaboratable
):
154 Merges data based on an address-match matrix.
155 Identifies (picks) one (any) row, then uses that row,
156 based on matching address bits, to merge (OR) all data
157 rows into the output.
159 Basically, by the time DataMerger is used, all of its incoming data is
160 determined not to conflict. The last step before actually submitting
161 the request to the Memory Subsystem is to work out which requests,
162 on the same 128-bit cache line, can be "merged" due to them being:
163 (A) on the same address (bits 4 and above) (B) having byte-enable
164 lines that (as previously mentioned) do not conflict.
166 Therefore, put simply, this module will:
167 (1) pick a row (any row) and identify it by an index labelled "idx"
168 (2) merge all byte-enable lines which are on that same address, as
169 indicated by addr_match_i[idx], onto the output
172 def __init__(self
, array_size
):
174 :addr_array_i: an NxN Array of Signals with bits set indicating address
175 match. bits across the diagonal (addr_array_i[x][x])
176 will always be set, to indicate "active".
177 :data_i: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit}
178 :data_o: an Output Record of same type
179 {data: 128 bit, byte_enable: 16 bit}
181 self
.array_size
= array_size
183 for i
in range(array_size
):
184 ul
.append(Signal(array_size
,
186 name
="addr_match_%d" % i
))
187 self
.addr_array_i
= Array(ul
)
190 for i
in range(array_size
):
191 ul
.append(DataMergerRecord())
192 self
.data_i
= Array(ul
)
193 self
.data_o
= DataMergerRecord()
195 def elaborate(self
, platform
):
199 m
.submodules
.pick
= pick
= PriorityEncoder(self
.array_size
)
200 for j
in range(self
.array_size
):
201 comb
+= pick
.i
[j
].eq(self
.addr_array_i
[j
].bool())
207 for j
in range(self
.array_size
):
208 select
= self
.addr_array_i
[idx
][j
]
209 r
= DataMergerRecord()
211 comb
+= r
.eq(self
.data_i
[j
])
213 comb
+= self
.data_o
.data
.eq(ortreereduce(l
,"data"))
214 comb
+= self
.data_o
.en
.eq(ortreereduce(l
,"en"))
219 class LDSTPort(Elaboratable
):
220 def __init__(self
, idx
, regwid
=64, addrwid
=48):
221 self
.pi
= PortInterface("ldst_port%d" % idx
, regwid
, addrwid
)
223 def elaborate(self
, platform
):
225 comb
, sync
= m
.d
.comb
, m
.d
.sync
228 m
.submodules
.busy_l
= busy_l
= SRLatch(False, name
="busy")
229 m
.submodules
.cyc_l
= cyc_l
= SRLatch(True, name
="cyc")
230 comb
+= cyc_l
.s
.eq(0)
231 comb
+= cyc_l
.r
.eq(0)
233 # this is a little weird: we let the L0Cache/Buffer set
234 # the outputs: this module just monitors "state".
236 # LD/ST requested activates "busy"
237 with m
.If(self
.pi
.is_ld_i | self
.pi
.is_st_i
):
238 comb
+= busy_l
.s
.eq(1)
240 # monitor for an exception or the completion of LD.
241 with m
.If(self
.pi
.addr_exc_o
):
242 comb
+= busy_l
.r
.eq(1)
244 # however ST needs one cycle before busy is reset
245 with m
.If(self
.pi
.st
.ok | self
.pi
.ld
.ok
):
246 comb
+= cyc_l
.s
.eq(1)
249 comb
+= cyc_l
.r
.eq(1)
250 comb
+= busy_l
.r
.eq(1)
252 # busy latch outputs to interface
253 comb
+= self
.pi
.busy_o
.eq(busy_l
.q
)
258 yield self
.pi
.is_ld_i
259 yield self
.pi
.is_st_i
260 yield from self
.pi
.op
.ports()
262 yield self
.pi
.go_die_i
263 yield from self
.pi
.addr
.ports()
264 yield self
.pi
.addr_ok_o
265 yield self
.pi
.addr_exc_o
267 yield from self
.pi
.ld
.ports()
268 yield from self
.pi
.st
.ports()
274 class L0CacheBuffer(Elaboratable
):
277 Note that the final version will have *two* interfaces per LDSTCompUnit,
278 to cover mis-aligned requests, as well as *two* 128-bit L1 Cache
279 interfaces: one for odd (addr[4] == 1) and one for even (addr[4] == 1).
281 This version is to be used for test purposes (and actively maintained
282 for such, rather than "replaced")
284 There are much better ways to implement this. However it's only
285 a "demo" / "test" class, and one important aspect: it responds
286 combinatorially, where a nmigen FSM's state-changes only activate
287 on clock-sync boundaries.
290 def __init__(self
, n_units
, mem
, regwid
=64, addrwid
=48):
291 self
.n_units
= n_units
294 for i
in range(n_units
):
295 ul
.append(LDSTPort(i
, regwid
, addrwid
))
296 self
.dports
= Array(ul
)
298 def elaborate(self
, platform
):
300 comb
, sync
= m
.d
.comb
, m
.d
.sync
302 # connect the ports as modules
303 for i
in range(self
.n_units
):
304 setattr(m
.submodules
, "port%d" % i
, self
.dports
[i
])
306 # state-machine latches
307 m
.submodules
.st_active
= st_active
= SRLatch(False, name
="st_active")
308 m
.submodules
.ld_active
= ld_active
= SRLatch(False, name
="ld_active")
309 m
.submodules
.reset_l
= reset_l
= SRLatch(True, name
="reset")
310 m
.submodules
.idx_l
= idx_l
= SRLatch(False, name
="idx_l")
311 m
.submodules
.adrok_l
= adrok_l
= SRLatch(False, name
="addr_acked")
313 # find one LD (or ST) and do it. only one per cycle.
314 # TODO: in the "live" (production) L0Cache/Buffer, merge multiple
315 # LD/STs using mask-expansion - see LenExpand class
317 m
.submodules
.ldpick
= ldpick
= PriorityEncoder(self
.n_units
)
318 m
.submodules
.stpick
= stpick
= PriorityEncoder(self
.n_units
)
320 lds
= Signal(self
.n_units
, reset_less
=True)
321 sts
= Signal(self
.n_units
, reset_less
=True)
324 for i
in range(self
.n_units
):
325 pi
= self
.dports
[i
].pi
326 ldi
.append(pi
.is_ld_i
& pi
.busy_o
) # accumulate ld-req signals
327 sti
.append(pi
.is_st_i
& pi
.busy_o
) # accumulate st-req signals
328 # put the requests into the priority-pickers
329 comb
+= ldpick
.i
.eq(Cat(*ldi
))
330 comb
+= stpick
.i
.eq(Cat(*sti
))
332 # hmm, have to select (record) the right port index
333 nbits
= log2_int(self
.n_units
, False)
334 ld_idx
= Signal(nbits
, reset_less
=False)
335 st_idx
= Signal(nbits
, reset_less
=False)
336 # use these because of the sync-and-comb pass-through capability
337 latchregister(m
, ldpick
.o
, ld_idx
, idx_l
.qn
, name
="ld_idx_l")
338 latchregister(m
, stpick
.o
, st_idx
, idx_l
.qn
, name
="st_idx_l")
340 # convenience variables to reference the "picked" port
341 ldport
= self
.dports
[ld_idx
].pi
342 stport
= self
.dports
[st_idx
].pi
343 # and the memory ports
344 rdport
= self
.mem
.rdport
345 wrport
= self
.mem
.wrport
347 # Priority-Pickers pick one and only one request, capture its index.
348 # from that point on this code *only* "listens" to that port.
350 sync
+= adrok_l
.s
.eq(0)
351 comb
+= adrok_l
.r
.eq(0)
352 with m
.If(~ldpick
.n
):
353 comb
+= ld_active
.s
.eq(1) # activate LD mode
354 comb
+= idx_l
.r
.eq(1) # pick (and capture) the port index
355 with m
.Elif(~stpick
.n
):
356 comb
+= st_active
.s
.eq(1) # activate ST mode
357 comb
+= idx_l
.r
.eq(1) # pick (and capture) the port index
359 # from this point onwards, with the port "picked", it stays picked
360 # until ld_active (or st_active) are de-asserted.
362 # if now in "LD" mode: wait for addr_ok, then send the address out
363 # to memory, acknowledge address, and send out LD data
364 with m
.If(ld_active
.q
):
365 with m
.If(ldport
.addr
.ok
& adrok_l
.qn
):
366 comb
+= rdport
.addr
.eq(ldport
.addr
.data
) # addr ok, send thru
367 comb
+= ldport
.addr_ok_o
.eq(1) # acknowledge addr ok
368 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
370 # if now in "ST" mode: likewise do the same but with "ST"
371 # to memory, acknowledge address, and send out LD data
372 with m
.If(st_active
.q
):
373 with m
.If(stport
.addr
.ok
):
374 comb
+= wrport
.addr
.eq(stport
.addr
.data
) # addr ok, send thru
375 with m
.If(adrok_l
.qn
):
376 comb
+= stport
.addr_ok_o
.eq(1) # acknowledge addr ok
377 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
379 # NOTE: in both these, below, the port itself takes care
380 # of de-asserting its "busy_o" signal, based on either ld.ok going
381 # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
383 # for LD mode, when addr has been "ok'd", assume that (because this
384 # is a "Memory" test-class) the memory read data is valid.
385 comb
+= reset_l
.s
.eq(0)
386 comb
+= reset_l
.r
.eq(0)
387 with m
.If(ld_active
.q
& adrok_l
.q
):
388 comb
+= ldport
.ld
.data
.eq(rdport
.data
) # put data out
389 comb
+= ldport
.ld
.ok
.eq(1) # indicate data valid
390 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
392 # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
393 with m
.If(st_active
.q
& stport
.st
.ok
):
394 comb
+= wrport
.data
.eq(stport
.st
.data
) # write st to mem
395 comb
+= wrport
.en
.eq(1) # enable write
396 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
398 # after waiting one cycle (reset_l is "sync" mode), reset the port
399 with m
.If(reset_l
.q
):
400 comb
+= idx_l
.s
.eq(1) # deactivate port-index selector
401 comb
+= ld_active
.r
.eq(1) # leave the ST active for 1 cycle
402 comb
+= st_active
.r
.eq(1) # leave the ST active for 1 cycle
403 comb
+= reset_l
.r
.eq(1) # clear reset
404 comb
+= adrok_l
.r
.eq(1) # address reset
409 for p
in self
.dports
:
413 class TstL0CacheBuffer(Elaboratable
):
414 def __init__(self
, n_units
=3, regwid
=16, addrwid
=4):
415 self
.mem
= TestMemory(regwid
, addrwid
)
416 self
.l0
= L0CacheBuffer(n_units
, self
.mem
, regwid
, addrwid
)
418 def elaborate(self
, platform
):
420 m
.submodules
.mem
= self
.mem
421 m
.submodules
.l0
= self
.l0
426 yield from self
.l0
.ports()
427 yield self
.mem
.rdport
.addr
428 yield self
.mem
.rdport
.data
429 yield self
.mem
.wrport
.addr
430 yield self
.mem
.wrport
.data
434 def wait_busy(port
, no
=False):
436 busy
= yield port
.pi
.busy_o
437 print("busy", no
, busy
)
445 addr_ok
= yield port
.pi
.addr_ok_o
446 print("addrok", addr_ok
)
454 ldok
= yield port
.pi
.ld
.ok
461 def l0_cache_st(dut
, addr
, data
):
467 # have to wait until not busy
468 yield from wait_busy(port1
, no
=False) # wait until not busy
470 # set up a ST on the port. address first:
471 yield port1
.pi
.is_st_i
.eq(1) # indicate LD
473 yield port1
.pi
.addr
.data
.eq(addr
) # set address
474 yield port1
.pi
.addr
.ok
.eq(1) # set ok
475 yield from wait_addr(port1
) # wait until addr ok
476 # yield # not needed, just for checking
477 # yield # not needed, just for checking
478 # assert "ST" for one cycle (required by the API)
479 yield port1
.pi
.st
.data
.eq(data
)
480 yield port1
.pi
.st
.ok
.eq(1)
482 yield port1
.pi
.st
.ok
.eq(0)
484 # can go straight to reset.
485 yield port1
.pi
.is_st_i
.eq(0) # end
486 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
487 # yield from wait_busy(port1, False) # wait until not busy
490 def l0_cache_ld(dut
, addr
, expected
):
497 # have to wait until not busy
498 yield from wait_busy(port1
, no
=False) # wait until not busy
500 # set up a LD on the port. address first:
501 yield port1
.pi
.is_ld_i
.eq(1) # indicate LD
503 yield port1
.pi
.addr
.data
.eq(addr
) # set address
504 yield port1
.pi
.addr
.ok
.eq(1) # set ok
505 yield from wait_addr(port1
) # wait until addr ok
507 yield from wait_ldok(port1
) # wait until ld ok
508 data
= yield port1
.pi
.ld
.data
511 yield port1
.pi
.is_ld_i
.eq(0) # end
512 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
513 # yield from wait_busy(port1, no=False) # wait until not busy
518 def l0_cache_ldst(dut
):
524 yield from l0_cache_st(dut
, 0x2, data
)
525 yield from l0_cache_st(dut
, 0x3, data2
)
526 result
= yield from l0_cache_ld(dut
, 0x2, data
)
527 result2
= yield from l0_cache_ld(dut
, 0x3, data2
)
529 assert data
== result
, "data %x != %x" % (result
, data
)
530 assert data2
== result2
, "data2 %x != %x" % (result2
, data2
)
532 def data_merger_merge(dut
):
538 dut
= TstL0CacheBuffer()
539 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
540 with
open("test_basic_l0_cache.il", "w") as f
:
543 run_simulation(dut
, l0_cache_ldst(dut
),
544 vcd_name
='test_l0_cache_basic.vcd')
546 def test_data_merger():
549 #vl = rtlil.convert(dut, ports=dut.ports())
550 #with open("test_data_merger.il", "w") as f:
553 run_simulation(dut
, data_merger_merge(dut
),
554 vcd_name
='test_data_merger.vcd')
557 if __name__
== '__main__':