src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
  14 from soc.fu.alu.alu_input_record import CompALUOpSubset
  15 from soc.fu.cr.cr_input_record import CompCROpSubset
  16 from soc.experiment.alu_hier import ALU, DummyALU
  17 from soc.experiment.compalu_multi import MultiCompUnit
  18 from soc.decoder.power_enums import MicrOp
  19 from nmutil.gtkw import write_gtkw
  20 from nmigen import Module, Signal
  21 from nmigen.cli import rtlil
  22
  23 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  24 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  25 from nmutil.sim_tmp_alternative import (Simulator, Settle, is_engine_pysim,
  26                                         Passive)
  27
  28
  29 def wrap(process):
  30     def wrapper():
  31         yield from process
  32     return wrapper
  33
  34
  35 class OperandProducer:
  36     """
  37     Produces an operand when requested by the Computation Unit
  38     (`dut` parameter), using the `rel_o` / `go_i` handshake.
  39
  40     Attaches itself to the `dut` operand indexed by `op_index`.
  41
  42     Has a programmable delay between the assertion of `rel_o` and the
  43     `go_i` pulse.
  44
  45     Data is presented only during the cycle in which `go_i` is active.
  46
  47     It adds itself as a passive process to the simulation (`sim` parameter).
  48     Since it is passive, it will not hang the simulation, and does not need a
  49     flag to terminate itself.
  50     """
  51     def __init__(self, sim, dut, op_index):
  52         self.count = Signal(8, name=f"src{op_index + 1}_count")
  53         """ transaction counter"""
  54         # data and handshake signals from the DUT
  55         self.port = dut.src_i[op_index]
  56         self.go_i = dut.rd.go_i[op_index]
  57         self.rel_o = dut.rd.rel_o[op_index]
  58         # transaction parameters, passed via signals
  59         self.delay = Signal(8)
  60         self.data = Signal.like(self.port)
  61         # add ourselves to the simulation process list
  62         sim.add_sync_process(self._process)
  63
  64     def _process(self):
  65         yield Passive()
  66         while True:
  67             # Settle() is needed to give a quick response to
  68             # the zero delay case
  69             yield Settle()
  70             # wait for rel_o to become active
  71             while not (yield self.rel_o):
  72                 yield
  73                 yield Settle()
  74             # read the transaction parameters
  75             delay = (yield self.delay)
  76             data = (yield self.data)
  77             # wait for `delay` cycles
  78             for _ in range(delay):
  79                 yield
  80             # activate go_i and present data, for one cycle
  81             yield self.go_i.eq(1)
  82             yield self.port.eq(data)
  83             yield self.count.eq(self.count + 1)
  84             yield
  85             yield self.go_i.eq(0)
  86             yield self.port.eq(0)
  87
  88     def send(self, data, delay):
  89         """
  90         Schedules the module to send some `data`, counting `delay` cycles after
  91         `rel_i` becomes active.
  92
  93         To be called from the main test-bench process,
  94         it returns in the same cycle.
  95
  96         Communication with the worker process is done by means of
  97         combinatorial simulation-only signals.
  98
  99         """
 100         yield self.data.eq(data)
 101         yield self.delay.eq(delay)
 102
 103
 104 class ResultConsumer:
 105     """
 106     Consumes a result when requested by the Computation Unit
 107     (`dut` parameter), using the `rel_o` / `go_i` handshake.
 108
 109     Attaches itself to the `dut` result indexed by `op_index`.
 110
 111     Has a programmable delay between the assertion of `rel_o` and the
 112     `go_i` pulse.
 113
 114     Data is retrieved only during the cycle in which `go_i` is active.
 115
 116     It adds itself as a passive process to the simulation (`sim` parameter).
 117     Since it is passive, it will not hang the simulation, and does not need a
 118     flag to terminate itself.
 119     """
 120     def __init__(self, sim, dut, op_index):
 121         self.count = Signal(8, name=f"dest{op_index + 1}_count")
 122         """ transaction counter"""
 123         # data and handshake signals from the DUT
 124         self.port = dut.dest[op_index]
 125         self.go_i = dut.wr.go_i[op_index]
 126         self.rel_o = dut.wr.rel_o[op_index]
 127         # transaction parameters, passed via signals
 128         self.delay = Signal(8)
 129         self.expected = Signal.like(self.port)
 130         # add ourselves to the simulation process list
 131         sim.add_sync_process(self._process)
 132
 133     def _process(self):
 134         yield Passive()
 135         while True:
 136             # Settle() is needed to give a quick response to
 137             # the zero delay case
 138             yield Settle()
 139             # wait for rel_o to become active
 140             while not (yield self.rel_o):
 141                 yield
 142                 yield Settle()
 143             # read the transaction parameters
 144             delay = (yield self.delay)
 145             expected = (yield self.expected)
 146             # wait for `delay` cycles
 147             for _ in range(delay):
 148                 yield
 149             # activate go_i for one cycle
 150             yield self.go_i.eq(1)
 151             yield self.count.eq(self.count + 1)
 152             yield
 153             # check received data against the expected value
 154             result = (yield self.port)
 155             assert result == expected,\
 156                 f"expected {expected}, received {result}"
 157             yield self.go_i.eq(0)
 158             yield self.port.eq(0)
 159
 160     def receive(self, expected, delay):
 161         """
 162         Schedules the module to receive some result,
 163         counting `delay` cycles after `rel_i` becomes active.
 164         As 'go_i' goes active, check the result with `expected`.
 165
 166         To be called from the main test-bench process,
 167         it returns in the same cycle.
 168
 169         Communication with the worker process is done by means of
 170         combinatorial simulation-only signals.
 171         """
 172         yield self.expected.eq(expected)
 173         yield self.delay.eq(delay)
 174
 175
 176 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 177     yield dut.issue_i.eq(0)
 178     yield
 179     yield dut.src_i[0].eq(a)
 180     yield dut.src_i[1].eq(b)
 181     yield dut.oper_i.insn_type.eq(op)
 182     yield dut.oper_i.invert_in.eq(inv_a)
 183     yield dut.oper_i.imm_data.data.eq(imm)
 184     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 185     yield dut.oper_i.zero_a.eq(zero_a)
 186     yield dut.issue_i.eq(1)
 187     yield
 188     yield dut.issue_i.eq(0)
 189     yield
 190     if not imm_ok or not zero_a:
 191         yield dut.rd.go_i.eq(0b11)
 192         while True:
 193             yield
 194             rd_rel_o = yield dut.rd.rel_o
 195             print("rd_rel", rd_rel_o)
 196             if rd_rel_o:
 197                 break
 198         yield dut.rd.go_i.eq(0)
 199     else:
 200         print("no go rd")
 201
 202     if len(dut.src_i) == 3:
 203         yield dut.rd.go_i.eq(0b100)
 204         while True:
 205             yield
 206             rd_rel_o = yield dut.rd.rel_o
 207             print("rd_rel", rd_rel_o)
 208             if rd_rel_o:
 209                 break
 210         yield dut.rd.go_i.eq(0)
 211     else:
 212         print("no 3rd rd")
 213
 214     req_rel_o = yield dut.wr.rel_o
 215     result = yield dut.data_o
 216     print("req_rel", req_rel_o, result)
 217     while True:
 218         req_rel_o = yield dut.wr.rel_o
 219         result = yield dut.data_o
 220         print("req_rel", req_rel_o, result)
 221         if req_rel_o:
 222             break
 223         yield
 224     yield dut.wr.go_i[0].eq(1)
 225     yield Settle()
 226     result = yield dut.data_o
 227     yield
 228     print("result", result)
 229     yield dut.wr.go_i[0].eq(0)
 230     yield
 231     return result
 232
 233
 234 def scoreboard_sim_fsm(dut, producers, consumers):
 235
 236     # stores the operation count
 237     op_count = 0
 238
 239     def op_sim_fsm(a, b, direction, expected, delays):
 240         print("op_sim_fsm", a, b, direction, expected)
 241         yield dut.issue_i.eq(0)
 242         yield
 243         # forward data and delays to the producers and consumers
 244         yield from producers[0].send(a, delays[0])
 245         yield from producers[1].send(b, delays[1])
 246         yield from consumers[0].receive(expected, delays[2])
 247         # submit operation, and assert issue_i for one cycle
 248         yield dut.oper_i.sdir.eq(direction)
 249         yield dut.issue_i.eq(1)
 250         yield
 251         yield dut.issue_i.eq(0)
 252         # wait for busy to be negated
 253         yield Settle()
 254         while (yield dut.busy_o):
 255             yield
 256             yield Settle()
 257         # update the operation count
 258         nonlocal op_count
 259         op_count = (op_count + 1) & 255
 260         # check that producers and consumers have the same count
 261         # this assures that no data was left unused or was lost
 262         assert (yield producers[0].count) == op_count
 263         assert (yield producers[1].count) == op_count
 264         assert (yield consumers[0].count) == op_count
 265
 266     # 13 >> 2 = 3
 267     # operand 1 arrives immediately
 268     # operand 2 arrives after operand 1
 269     # write data is accepted immediately
 270     yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
 271     # 3 << 4 = 48
 272     # operand 2 arrives immediately
 273     # operand 1 arrives after operand 2
 274     # write data is accepted after some delay
 275     yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
 276     # 21 << 0 = 21
 277     # operands 1 and 2 arrive at the same time
 278     # write data is accepted after some delay
 279     yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
 280
 281
 282 def scoreboard_sim_dummy(op):
 283     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 284                         src_delays=[0, 2, 1], dest_delays=[0])
 285     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 286                         src_delays=[2, 1, 0], dest_delays=[2])
 287     # test all combinations of masked input ports
 288     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [0],
 289                         rdmaskn=[1, 0, 0],
 290                         src_delays=[0, 2, 1], dest_delays=[0])
 291     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 292                         rdmaskn=[0, 1, 0],
 293                         src_delays=[2, 1, 0], dest_delays=[2])
 294     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 295                         rdmaskn=[0, 0, 1],
 296                         src_delays=[2, 1, 0], dest_delays=[2])
 297     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 298                         rdmaskn=[0, 1, 1],
 299                         src_delays=[2, 1, 0], dest_delays=[2])
 300     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
 301                         rdmaskn=[1, 1, 0],
 302                         src_delays=[2, 1, 0], dest_delays=[2])
 303     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
 304                         rdmaskn=[1, 1, 1],
 305                         src_delays=[2, 1, 0], dest_delays=[2])
 306
 307
 308 class OpSim:
 309     """ALU Operation issuer
 310
 311     Issues operations to the DUT"""
 312     def __init__(self, dut, sim):
 313         self.op_count = 0
 314         self.zero_a_count = 0
 315         self.imm_ok_count = 0
 316         self.rdmaskn_count = [0] * len(dut.src_i)
 317         self.dut = dut
 318         # create one operand producer for each input port
 319         self.producers = list()
 320         for i in range(len(dut.src_i)):
 321             self.producers.append(OperandProducer(sim, dut, i))
 322         # create one result consumer for each output port
 323         self.consumers = list()
 324         for i in range(len(dut.dest)):
 325             self.consumers.append(ResultConsumer(sim, dut, i))
 326     def issue(self, src_i, op, expected, src_delays, dest_delays,
 327               inv_a=0, imm=0, imm_ok=0, zero_a=0, rdmaskn=None):
 328         """Executes the issue operation"""
 329         dut = self.dut
 330         producers = self.producers
 331         consumers = self.consumers
 332         if rdmaskn is None:
 333             rdmaskn = [0] * len(src_i)
 334         yield dut.issue_i.eq(0)
 335         yield
 336         # forward data and delays to the producers and consumers
 337         # first, send special cases (with zero_a and/or imm_ok)
 338         if not zero_a:
 339             yield from producers[0].send(src_i[0], src_delays[0])
 340         if not imm_ok:
 341             yield from producers[1].send(src_i[1], src_delays[1])
 342         # then, send the rest (if any)
 343         for i in range(2, len(producers)):
 344             yield from producers[i].send(src_i[i], src_delays[i])
 345         for i in range(len(consumers)):
 346             yield from consumers[i].receive(expected[i], dest_delays[i])
 347         # submit operation, and assert issue_i for one cycle
 348         yield dut.oper_i.insn_type.eq(op)
 349         if hasattr(dut.oper_i, "invert_in"):
 350             yield dut.oper_i.invert_in.eq(inv_a)
 351         if hasattr(dut.oper_i, "imm_data"):
 352             yield dut.oper_i.imm_data.data.eq(imm)
 353             yield dut.oper_i.imm_data.ok.eq(imm_ok)
 354         if hasattr(dut.oper_i, "zero_a"):
 355             yield dut.oper_i.zero_a.eq(zero_a)
 356         if hasattr(dut, "rdmaskn"):
 357             rdmaskn_bits = 0
 358             for i in range(len(rdmaskn)):
 359                 rdmaskn_bits |= rdmaskn[i] << i
 360             yield dut.rdmaskn.eq(rdmaskn_bits)
 361         yield dut.issue_i.eq(1)
 362         yield
 363         yield dut.issue_i.eq(0)
 364         # deactivate decoder inputs along with issue_i, so we can be sure they
 365         # were latched at the correct cycle
 366         # note: rdmaskn is not latched, and must be held as long as
 367         # busy_o is active
 368         # todo: is the above restriction on rdmaskn intentional?
 369         # todo: shouldn't it be latched by issue_i, like the others?
 370         yield self.dut.oper_i.insn_type.eq(0)
 371         if hasattr(dut.oper_i, "invert_in"):
 372             yield self.dut.oper_i.invert_in.eq(0)
 373         if hasattr(dut.oper_i, "imm_data"):
 374             yield self.dut.oper_i.imm_data.data.eq(0)
 375             yield self.dut.oper_i.imm_data.ok.eq(0)
 376         if hasattr(dut.oper_i, "zero_a"):
 377             yield self.dut.oper_i.zero_a.eq(0)
 378         # wait for busy to be negated
 379         yield Settle()
 380         while (yield dut.busy_o):
 381             yield
 382             yield Settle()
 383         # now, deactivate rdmaskn
 384         if hasattr(dut, "rdmaskn"):
 385             yield dut.rdmaskn.eq(0)
 386         # update the operation count
 387         self.op_count = (self.op_count + 1) & 255
 388         # On zero_a, imm_ok and rdmaskn executions, the producer counters will
 389         # fall behind. But, by summing the following counts, the invariant is
 390         # preserved.
 391         if zero_a and not rdmaskn[0]:
 392             self.zero_a_count = self.zero_a_count + 1
 393         if imm_ok and not rdmaskn[1]:
 394             self.imm_ok_count = self.imm_ok_count + 1
 395         for i in range(len(rdmaskn)):
 396             if rdmaskn[i]:
 397                 self.rdmaskn_count[i] = self.rdmaskn_count[i] + 1
 398         # check that producers and consumers have the same count
 399         # this assures that no data was left unused or was lost
 400         # first, check special cases (zero_a and imm_ok)
 401         port_a_cnt = \
 402             (yield producers[0].count) \
 403             + self.zero_a_count \
 404             + self.rdmaskn_count[0]
 405         port_b_cnt = \
 406             (yield producers[1].count) \
 407             + self.imm_ok_count \
 408             + self.rdmaskn_count[1]
 409         assert port_a_cnt == self.op_count
 410         assert port_b_cnt == self.op_count
 411         # then, check the rest (if any)
 412         for i in range(2, len(producers)):
 413             port_cnt = (yield producers[i].count) + self.rdmaskn_count[i]
 414             assert port_cnt == self.op_count
 415         # check write counter
 416         for i in range(len(consumers)):
 417             assert (yield consumers[i].count) == self.op_count
 418
 419
 420 def scoreboard_sim(op):
 421     # zero (no) input operands test
 422     # 0 + 8 = 8
 423     yield from op.issue([5, 2], MicrOp.OP_ADD, [8],
 424                         zero_a=1, imm=8, imm_ok=1,
 425                         src_delays=[0, 2], dest_delays=[0])
 426     # 5 + 8 = 13
 427     yield from op.issue([5, 2], MicrOp.OP_ADD, [13],
 428                         inv_a=0, imm=8, imm_ok=1,
 429                         src_delays=[2, 0], dest_delays=[2])
 430     # 5 + 2 = 7
 431     yield from op.issue([5, 2], MicrOp.OP_ADD, [7],
 432                         src_delays=[1, 1], dest_delays=[1])
 433     # (-6) + 2 = (-4)
 434     yield from op.issue([5, 2], MicrOp.OP_ADD, [65532],
 435                         inv_a=1,
 436                         src_delays=[1, 2], dest_delays=[0])
 437     # 0 + 2 = 2
 438     yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
 439                         zero_a=1,
 440                         src_delays=[2, 0], dest_delays=[1])
 441
 442     # test combinatorial zero-delay operation
 443     # In the test ALU, any operation other than ADD, MUL or SHR
 444     # is zero-delay, and do a subtraction.
 445     # 5 - 2 = 3
 446     yield from op.issue([5, 2], MicrOp.OP_NOP, [3],
 447                         src_delays=[0, 1], dest_delays=[2])
 448     # test all combinations of masked input ports
 449     # 5 + 0 (masked) = 5
 450     yield from op.issue([5, 2], MicrOp.OP_ADD, [5],
 451                         rdmaskn=[0, 1],
 452                         src_delays=[2, 1], dest_delays=[0])
 453     # 0 (masked) + 2 = 2
 454     yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
 455                         rdmaskn=[1, 0],
 456                         src_delays=[1, 2], dest_delays=[1])
 457     # 0 (masked) + 0 (masked) = 0
 458     yield from op.issue([5, 2], MicrOp.OP_ADD, [0],
 459                         rdmaskn=[1, 1],
 460                         src_delays=[1, 2], dest_delays=[1])
 461
 462
 463 def test_compunit_fsm():
 464     style = {
 465         'in': {'color': 'orange'},
 466         'out': {'color': 'yellow'},
 467     }
 468     traces = [
 469         'clk',
 470         ('operation port', {'color': 'red'}, [
 471             'cu_issue_i', 'cu_busy_o',
 472             {'comment': 'operation'},
 473             'oper_i_None__sdir']),
 474         ('operand 1 port', 'in', [
 475             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 476             ('cu_rd__go_i[1:0]', {'bit': 1}),
 477             'src1_i[7:0]']),
 478         ('operand 2 port', 'in', [
 479             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 480             ('cu_rd__go_i[1:0]', {'bit': 0}),
 481             'src2_i[7:0]']),
 482         ('result port', 'out', [
 483             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
 484         ('alu', {'submodule': 'alu'}, [
 485             ('prev port', 'in', [
 486                 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
 487                 ({'submodule': 'p'},
 488                     ['p_valid_i', 'p_ready_o'])]),
 489             ('next port', 'out', [
 490                 'n_data_o[7:0]',
 491                 ({'submodule': 'n'},
 492                     ['n_valid_o', 'n_ready_i'])])]),
 493         ('debug', {'module': 'top'},
 494             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 495
 496     write_gtkw(
 497         "test_compunit_fsm1.gtkw",
 498         "test_compunit_fsm1.vcd",
 499         traces, style,
 500         module='top.cu'
 501     )
 502     m = Module()
 503     alu = Shifter(8)
 504     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
 505     m.submodules.cu = dut
 506
 507     vl = rtlil.convert(dut, ports=dut.ports())
 508     with open("test_compunit_fsm1.il", "w") as f:
 509         f.write(vl)
 510
 511     sim = Simulator(m)
 512     sim.add_clock(1e-6)
 513
 514     # create one operand producer for each input port
 515     prod_a = OperandProducer(sim, dut, 0)
 516     prod_b = OperandProducer(sim, dut, 1)
 517     # create an result consumer for the output port
 518     cons = ResultConsumer(sim, dut, 0)
 519     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 520                                                  [prod_a, prod_b],
 521                                                  [cons])))
 522     sim_writer = sim.write_vcd('test_compunit_fsm1.vcd',
 523                                traces=[prod_a.count,
 524                                        prod_b.count,
 525                                        cons.count])
 526     with sim_writer:
 527         sim.run()
 528
 529
 530 def test_compunit():
 531
 532     m = Module()
 533     alu = ALU(16)
 534     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 535     m.submodules.cu = dut
 536
 537     vl = rtlil.convert(dut, ports=dut.ports())
 538     with open("test_compunit1.il", "w") as f:
 539         f.write(vl)
 540
 541     sim = Simulator(m)
 542     sim.add_clock(1e-6)
 543
 544     # create an operation issuer
 545     op = OpSim(dut, sim)
 546     sim.add_sync_process(wrap(scoreboard_sim(op)))
 547     sim_writer = sim.write_vcd('test_compunit1.vcd')
 548     with sim_writer:
 549         sim.run()
 550
 551
 552 class CompUnitParallelTest:
 553     def __init__(self, dut):
 554         self.dut = dut
 555
 556         # Operation cycle should not take longer than this:
 557         self.MAX_BUSY_WAIT = 50
 558
 559         # Minimum duration in which issue_i will be kept inactive,
 560         # during which busy_o must remain low.
 561         self.MIN_BUSY_LOW = 5
 562
 563         # Number of cycles to stall until the assertion of go.
 564         # One value, for each port. Can be zero, for no delay.
 565         self.RD_GO_DELAY = [0, 3]
 566
 567         # store common data for the input operation of the processes
 568         # input operation:
 569         self.op = 0
 570         self.inv_a = self.zero_a = 0
 571         self.imm = self.imm_ok = 0
 572         self.imm_control = (0, 0)
 573         self.rdmaskn = (0, 0)
 574         # input data:
 575         self.operands = (0, 0)
 576
 577         # Indicates completion of the sub-processes
 578         self.rd_complete = [False, False]
 579
 580     def driver(self):
 581         print("Begin parallel test.")
 582         yield from self.operation(5, 2, MicrOp.OP_ADD)
 583
 584     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
 585                   rdmaskn=(0, 0)):
 586         # store data for the operation
 587         self.operands = (a, b)
 588         self.op = op
 589         self.inv_a = inv_a
 590         self.imm = imm
 591         self.imm_ok = imm_ok
 592         self.zero_a = zero_a
 593         self.imm_control = (zero_a, imm_ok)
 594         self.rdmaskn = rdmaskn
 595
 596         # Initialize completion flags
 597         self.rd_complete = [False, False]
 598
 599         # trigger operation cycle
 600         yield from self.issue()
 601
 602         # check that the sub-processes completed, before the busy_o cycle ended
 603         for completion in self.rd_complete:
 604             assert completion
 605
 606     def issue(self):
 607         # issue_i starts inactive
 608         yield self.dut.issue_i.eq(0)
 609
 610         for n in range(self.MIN_BUSY_LOW):
 611             yield
 612             # busy_o must remain inactive. It cannot rise on its own.
 613             busy_o = yield self.dut.busy_o
 614             assert not busy_o
 615
 616         # activate issue_i to begin the operation cycle
 617         yield self.dut.issue_i.eq(1)
 618
 619         # at the same time, present the operation
 620         yield self.dut.oper_i.insn_type.eq(self.op)
 621         yield self.dut.oper_i.invert_in.eq(self.inv_a)
 622         yield self.dut.oper_i.imm_data.data.eq(self.imm)
 623         yield self.dut.oper_i.imm_data.ok.eq(self.imm_ok)
 624         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 625         rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1)
 626         yield self.dut.rdmaskn.eq(rdmaskn)
 627
 628         # give one cycle for the CompUnit to latch the data
 629         yield
 630
 631         # busy_o must keep being low in this cycle, because issue_i was
 632         # low on the previous cycle.
 633         # It cannot rise on its own.
 634         # Also, busy_o and issue_i must never be active at the same time, ever.
 635         busy_o = yield self.dut.busy_o
 636         assert not busy_o
 637
 638         # Lower issue_i
 639         yield self.dut.issue_i.eq(0)
 640
 641         # deactivate inputs along with issue_i, so we can be sure the data
 642         # was latched at the correct cycle
 643         # note: rdmaskn must be held, while busy_o is active
 644         # TODO: deactivate rdmaskn when the busy_o cycle ends
 645         yield self.dut.oper_i.insn_type.eq(0)
 646         yield self.dut.oper_i.invert_in.eq(0)
 647         yield self.dut.oper_i.imm_data.data.eq(0)
 648         yield self.dut.oper_i.imm_data.ok.eq(0)
 649         yield self.dut.oper_i.zero_a.eq(0)
 650         yield
 651
 652         # wait for busy_o to lower
 653         # timeout after self.MAX_BUSY_WAIT cycles
 654         for n in range(self.MAX_BUSY_WAIT):
 655             # sample busy_o in the current cycle
 656             busy_o = yield self.dut.busy_o
 657             if not busy_o:
 658                 # operation cycle ends when busy_o becomes inactive
 659                 break
 660             yield
 661
 662         # if busy_o is still active, a timeout has occurred
 663         # TODO: Uncomment this, once the test is complete:
 664         # assert not busy_o
 665
 666         if busy_o:
 667             print("If you are reading this, "
 668                   "it's because the above test failed, as expected,\n"
 669                   "with a timeout. It must pass, once the test is complete.")
 670             return
 671
 672         print("If you are reading this, "
 673               "it's because the above test unexpectedly passed.")
 674
 675     def rd(self, rd_idx):
 676         # wait for issue_i to rise
 677         while True:
 678             issue_i = yield self.dut.issue_i
 679             if issue_i:
 680                 break
 681             # issue_i has not risen yet, so rd must keep low
 682             rel = yield self.dut.rd.rel_o[rd_idx]
 683             assert not rel
 684             yield
 685
 686         # we do not want rd to rise on an immediate operand
 687         # if it is immediate, exit the process
 688         # likewise, if the read mask is active
 689         # TODO: don't exit the process, monitor rd instead to ensure it
 690         #       doesn't rise on its own
 691         if self.rdmaskn[rd_idx] or self.imm_control[rd_idx]:
 692             self.rd_complete[rd_idx] = True
 693             return
 694
 695         # issue_i has risen. rel must rise on the next cycle
 696         rel = yield self.dut.rd.rel_o[rd_idx]
 697         assert not rel
 698
 699         # stall for additional cycles. Check that rel doesn't fall on its own
 700         for n in range(self.RD_GO_DELAY[rd_idx]):
 701             yield
 702             rel = yield self.dut.rd.rel_o[rd_idx]
 703             assert rel
 704
 705         # Before asserting "go", make sure "rel" has risen.
 706         # The use of Settle allows "go" to be set combinatorially,
 707         # rising on the same cycle as "rel".
 708         yield Settle()
 709         rel = yield self.dut.rd.rel_o[rd_idx]
 710         assert rel
 711
 712         # assert go for one cycle, passing along the operand value
 713         yield self.dut.rd.go_i[rd_idx].eq(1)
 714         yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
 715         # check that the operand was sent to the alu
 716         # TODO: Properly check the alu protocol
 717         yield Settle()
 718         alu_input = yield self.dut.get_in(rd_idx)
 719         assert alu_input == self.operands[rd_idx]
 720         yield
 721
 722         # rel must keep high, since go was inactive in the last cycle
 723         rel = yield self.dut.rd.rel_o[rd_idx]
 724         assert rel
 725
 726         # finish the go one-clock pulse
 727         yield self.dut.rd.go_i[rd_idx].eq(0)
 728         yield self.dut.src_i[rd_idx].eq(0)
 729         yield
 730
 731         # rel must have gone low in response to go being high
 732         # on the previous cycle
 733         rel = yield self.dut.rd.rel_o[rd_idx]
 734         assert not rel
 735
 736         self.rd_complete[rd_idx] = True
 737
 738         # TODO: check that rel doesn't rise again until the end of the
 739         #       busy_o cycle
 740
 741     def wr(self, wr_idx):
 742         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 743         yield
 744         # TODO: also when dut.wr.go is set, check the output against the
 745         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 746
 747     def run_simulation(self, vcd_name):
 748         m = Module()
 749         m.submodules.cu = self.dut
 750         sim = Simulator(m)
 751         sim.add_clock(1e-6)
 752
 753         sim.add_sync_process(wrap(self.driver()))
 754         sim.add_sync_process(wrap(self.rd(0)))
 755         sim.add_sync_process(wrap(self.rd(1)))
 756         sim.add_sync_process(wrap(self.wr(0)))
 757         sim_writer = sim.write_vcd(vcd_name)
 758         with sim_writer:
 759             sim.run()
 760
 761
 762 def test_compunit_regspec2_fsm():
 763
 764     inspec = [('INT', 'data', '0:15'),
 765               ('INT', 'shift', '0:15')]
 766     outspec = [('INT', 'data', '0:15')]
 767
 768     regspec = (inspec, outspec)
 769
 770     m = Module()
 771     alu = Shifter(8)
 772     dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
 773     m.submodules.cu = dut
 774
 775     sim = Simulator(m)
 776     sim.add_clock(1e-6)
 777
 778     # create one operand producer for each input port
 779     prod_a = OperandProducer(sim, dut, 0)
 780     prod_b = OperandProducer(sim, dut, 1)
 781     # create an result consumer for the output port
 782     cons = ResultConsumer(sim, dut, 0)
 783     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 784                                                  [prod_a, prod_b],
 785                                                  [cons])))
 786     sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd',
 787                                traces=[prod_a.count,
 788                                        prod_b.count,
 789                                        cons.count])
 790     with sim_writer:
 791         sim.run()
 792
 793
 794 def test_compunit_regspec3():
 795
 796     style = {
 797         'in': {'color': 'orange'},
 798         'out': {'color': 'yellow'},
 799     }
 800     traces = [
 801         'clk',
 802         ('operation port', {'color': 'red'}, [
 803             'cu_issue_i', 'cu_busy_o',
 804             {'comment': 'operation'},
 805             ('oper_i_None__insn_type'
 806              + ('' if is_engine_pysim() else '[6:0]'),
 807              {'display': 'insn_type'})]),
 808         ('operand 1 port', 'in', [
 809             ('cu_rd__rel_o[2:0]', {'bit': 2}),
 810             ('cu_rd__go_i[2:0]', {'bit': 2}),
 811             'src1_i[15:0]']),
 812         ('operand 2 port', 'in', [
 813             ('cu_rd__rel_o[2:0]', {'bit': 1}),
 814             ('cu_rd__go_i[2:0]', {'bit': 1}),
 815             'src2_i[15:0]']),
 816         ('operand 3 port', 'in', [
 817             ('cu_rd__rel_o[2:0]', {'bit': 0}),
 818             ('cu_rd__go_i[2:0]', {'bit': 0}),
 819             'src1_i[15:0]']),
 820         ('result port', 'out', [
 821             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 822         ('alu', {'submodule': 'alu'}, [
 823             ('prev port', 'in', [
 824                 'oper_i_None__insn_type', 'i1[15:0]',
 825                 'valid_i', 'ready_o']),
 826             ('next port', 'out', [
 827                 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
 828
 829     write_gtkw("test_compunit_regspec3.gtkw",
 830                "test_compunit_regspec3.vcd",
 831                traces, style,
 832                clk_period=1e-6,
 833                module='top.cu')
 834
 835     inspec = [('INT', 'a', '0:15'),
 836               ('INT', 'b', '0:15'),
 837               ('INT', 'c', '0:15')]
 838     outspec = [('INT', 'o', '0:15')]
 839
 840     regspec = (inspec, outspec)
 841
 842     m = Module()
 843     alu = DummyALU(16)
 844     dut = MultiCompUnit(regspec, alu, CompCROpSubset)
 845     m.submodules.cu = dut
 846
 847     sim = Simulator(m)
 848     sim.add_clock(1e-6)
 849
 850     # create an operation issuer
 851     op = OpSim(dut, sim)
 852     sim.add_sync_process(wrap(scoreboard_sim_dummy(op)))
 853     sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
 854     with sim_writer:
 855         sim.run()
 856
 857
 858 def test_compunit_regspec1():
 859
 860     style = {
 861         'in': {'color': 'orange'},
 862         'out': {'color': 'yellow'},
 863     }
 864     traces = [
 865         'clk',
 866         ('operation port', {'color': 'red'}, [
 867             'cu_issue_i', 'cu_busy_o',
 868             {'comment': 'operation'},
 869             ('oper_i_None__insn_type'
 870              + ('' if is_engine_pysim() else '[6:0]'),
 871              {'display': 'insn_type'}),
 872             ('oper_i_None__invert_in', {'display': 'invert_in'}),
 873             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
 874             ('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),
 875             ('oper_i_None__zero_a', {'display': 'zero_a'})]),
 876         ('operand 1 port', 'in', [
 877             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 878             ('cu_rd__go_i[1:0]', {'bit': 1}),
 879             'src1_i[15:0]']),
 880         ('operand 2 port', 'in', [
 881             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 882             ('cu_rd__go_i[1:0]', {'bit': 0}),
 883             'src2_i[15:0]']),
 884         ('result port', 'out', [
 885             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 886         ('alu', {'submodule': 'alu'}, [
 887             ('prev port', 'in', [
 888                 'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
 889                 'valid_i', 'ready_o']),
 890             ('next port', 'out', [
 891                 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
 892         ('debug', {'module': 'top'},
 893             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 894
 895     write_gtkw("test_compunit_regspec1.gtkw",
 896                "test_compunit_regspec1.vcd",
 897                traces, style,
 898                clk_period=1e-6,
 899                module='top.cu')
 900
 901     inspec = [('INT', 'a', '0:15'),
 902               ('INT', 'b', '0:15')]
 903     outspec = [('INT', 'o', '0:15')]
 904
 905     regspec = (inspec, outspec)
 906
 907     m = Module()
 908     alu = ALU(16)
 909     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 910     m.submodules.cu = dut
 911
 912     vl = rtlil.convert(dut, ports=dut.ports())
 913     with open("test_compunit_regspec1.il", "w") as f:
 914         f.write(vl)
 915
 916     sim = Simulator(m)
 917     sim.add_clock(1e-6)
 918
 919     # create an operation issuer
 920     op = OpSim(dut, sim)
 921     sim.add_sync_process(wrap(scoreboard_sim(op)))
 922     sim_writer = sim.write_vcd('test_compunit_regspec1.vcd',
 923                                traces=[op.producers[0].count,
 924                                        op.producers[1].count,
 925                                        op.consumers[0].count])
 926     with sim_writer:
 927         sim.run()
 928
 929     test = CompUnitParallelTest(dut)
 930     test.run_simulation("test_compunit_parallel.vcd")
 931
 932
 933 if __name__ == '__main__':
 934     test_compunit()
 935     test_compunit_fsm()
 936     test_compunit_regspec1()
 937     test_compunit_regspec2_fsm()
 938     test_compunit_regspec3()