src/soc/experiment/test/test_ldst_pi.py

   1 """MMU PortInterface Test
   2
   3 quite basic, goes directly to the MMU to assert signals (does not
   4 yet use PortInterface)
   5 """
   6
   7 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   8 from nmigen.cli import main
   9 from nmigen.cli import rtlil
  10 from nmutil.mask import Mask, masked
  11 from nmutil.util import Display
  12
  13 if True:
  14     from nmigen.back.pysim import Simulator, Delay, Settle
  15 else:
  16     from nmigen.sim.cxxsim import Simulator, Delay, Settle
  17 from nmutil.util import wrap
  18
  19 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.config.loadstore import ConfigMemoryPortInterface
  22
  23 from soc.fu.ldst.loadstore import LoadStore1
  24 from soc.experiment.mmu import MMU
  25
  26 from nmigen.compat.sim import run_simulation
  27
  28
  29 stop = False
  30
  31 def wb_get(wb):
  32     """simulator process for getting memory load requests
  33     """
  34
  35     global stop
  36
  37     def b(x):
  38         return int.from_bytes(x.to_bytes(8, byteorder='little'),
  39                               byteorder='big', signed=False)
  40
  41     mem = {0x10000:    # PARTITION_TABLE_2
  42                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
  43            b(0x800000000100000b),
  44
  45            0x30000:     # RADIX_ROOT_PTE
  46                         # V = 1 L = 0 NLB = 0x400 NLS = 9
  47            b(0x8000000000040009),
  48
  49            0x40000:     # RADIX_SECOND_LEVEL
  50                         #          V = 1 L = 1 SW = 0 RPN = 0
  51                            # R = 1 C = 1 ATT = 0 EAA 0x7
  52            b(0xc000000000000187),
  53
  54           0x1000000:   # PROCESS_TABLE_3
  55                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
  56            b(0x40000000000300ad),
  57           }
  58
  59     while not stop:
  60         while True: # wait for dc_valid
  61             if stop:
  62                 return
  63             cyc = yield (wb.cyc)
  64             stb = yield (wb.stb)
  65             if cyc and stb:
  66                 break
  67             yield
  68         addr = (yield wb.adr) << 3
  69         if addr not in mem:
  70             print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
  71
  72         data = mem.get(addr, 0)
  73         yield wb.dat_r.eq(data)
  74         print ("    DCACHE get %x data %x" % (addr, data))
  75         yield wb.ack.eq(1)
  76         yield
  77         yield wb.ack.eq(0)
  78
  79
  80 def mmu_lookup(dut, addr):
  81     mmu = dut.submodules.mmu
  82     global stop
  83
  84     print("pi_ld")
  85     yield from pi_ld(dut.submodules.ldst.pi, addr, 1, msr_pr=1)
  86     print("pi_ld done")
  87     """
  88     # original test code kept for reference
  89     while not stop: # wait for dc_valid / err
  90         print("waiting for mmu")
  91         l_done = yield (mmu.l_out.done)
  92         l_err = yield (mmu.l_out.err)
  93         l_badtree = yield (mmu.l_out.badtree)
  94         l_permerr = yield (mmu.l_out.perm_error)
  95         l_rc_err = yield (mmu.l_out.rc_error)
  96         l_segerr = yield (mmu.l_out.segerr)
  97         l_invalid = yield (mmu.l_out.invalid)
  98         if (l_done or l_err or l_badtree or
  99             l_permerr or l_rc_err or l_segerr or l_invalid):
 100             break
 101         yield
 102     """
 103     phys_addr = yield mmu.d_out.addr
 104     pte = yield mmu.d_out.pte
 105     l_done = yield (mmu.l_out.done)
 106     l_err = yield (mmu.l_out.err)
 107     l_badtree = yield (mmu.l_out.badtree)
 108     print ("translated done %d err %d badtree %d addr %x pte %x" % \
 109                (l_done, l_err, l_badtree, phys_addr, pte))
 110     yield
 111     yield mmu.l_in.valid.eq(0)
 112
 113     return phys_addr
 114
 115
 116 def ldst_sim(dut):
 117     mmu = dut.submodules.mmu
 118     global stop
 119     yield mmu.rin.prtbl.eq(0x1000000) # set process table
 120     yield
 121
 122     addr = 0x1000
 123     print("pi_ld")
 124
 125     # TODO mmu_lookup using port interface
 126     # set inputs
 127     phys_addr = yield from mmu_lookup(dut, addr)
 128     assert phys_addr == 0x40000
 129
 130     phys_addr = yield from mmu_lookup(dut, addr)
 131     assert phys_addr == 0x40000
 132
 133     stop = True
 134
 135
 136 def test_mmu():
 137
 138     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 139                          imem_ifacetype='',
 140                          addr_wid=48,
 141                          #disable_cache=True, # hmmm...
 142                          mask_wid=8,
 143                          reg_wid=64)
 144
 145     m = Module()
 146     comb = m.d.comb
 147     cmpi = ConfigMemoryPortInterface(pspec)
 148     m.submodules.ldst = ldst = cmpi.pi
 149     m.submodules.mmu = mmu = MMU()
 150     dcache = ldst.dcache
 151
 152     l_in, l_out = mmu.l_in, mmu.l_out
 153     d_in, d_out = dcache.d_in, dcache.d_out
 154     wb_out, wb_in = dcache.wb_out, dcache.wb_in
 155
 156     # link mmu and dcache together
 157     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 158     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 159
 160     # link ldst and MMU together
 161     comb += l_in.eq(ldst.m_out)
 162     comb += ldst.m_in.eq(l_out)
 163
 164
 165     # nmigen Simulation
 166     sim = Simulator(m)
 167     sim.add_clock(1e-6)
 168
 169     sim.add_sync_process(wrap(ldst_sim(m)))
 170     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus())))
 171     with sim.write_vcd('test_ldst_pi.vcd'):
 172         sim.run()
 173
 174
 175 if __name__ == '__main__':
 176     test_mmu()