src/soc/fu/alu/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.alu.pipeline import ALUBasePipe
  16 from soc.fu.alu.pipe_data import ALUPipeSpec
  17 import random
  18
  19 class TestCase:
  20     def __init__(self, program, regs, sprs, name):
  21         self.program = program
  22         self.regs = regs
  23         self.sprs = sprs
  24         self.name = name
  25
  26
  27 def set_alu_inputs(alu, dec2, sim):
  28     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  29     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  30     # and place it into data_i.b
  31
  32     reg1_ok = yield dec2.e.read_reg1.ok
  33     if reg1_ok:
  34         data1 = yield dec2.e.read_reg1.data
  35         data1 = sim.gpr(data1).value
  36     else:
  37         data1 = 0
  38
  39     yield alu.p.data_i.a.eq(data1)
  40
  41     # If there's an immediate, set the B operand to that
  42     reg2_ok = yield dec2.e.read_reg2.ok
  43     imm_ok = yield dec2.e.imm_data.imm_ok
  44     if imm_ok:
  45         data2 = yield dec2.e.imm_data.imm
  46     elif reg2_ok:
  47         data2 = yield dec2.e.read_reg2.data
  48         data2 = sim.gpr(data2).value
  49     else:
  50         data2 = 0
  51     yield alu.p.data_i.b.eq(data2)
  52
  53
  54
  55 def set_extra_alu_inputs(alu, dec2, sim):
  56     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  57     carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  58     yield alu.p.data_i.xer_ca[0].eq(carry)
  59     yield alu.p.data_i.xer_ca[1].eq(carry32)
  60     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  61     yield alu.p.data_i.xer_so.eq(so)
  62
  63
  64 # This test bench is a bit different than is usual. Initially when I
  65 # was writing it, I had all of the tests call a function to create a
  66 # device under test and simulator, initialize the dut, run the
  67 # simulation for ~2 cycles, and assert that the dut output what it
  68 # should have. However, this was really slow, since it needed to
  69 # create and tear down the dut and simulator for every test case.
  70
  71 # Now, instead of doing that, every test case in ALUTestCase puts some
  72 # data into the test_data list below, describing the instructions to
  73 # be tested and the initial state. Once all the tests have been run,
  74 # test_data gets passed to TestRunner which then sets up the DUT and
  75 # simulator once, runs all the data through it, and asserts that the
  76 # results match the pseudocode sim at every cycle.
  77
  78 # By doing this, I've reduced the time it takes to run the test suite
  79 # massively. Before, it took around 1 minute on my computer, now it
  80 # takes around 3 seconds
  81
  82 test_data = []
  83
  84
  85 class ALUTestCase(FHDLTestCase):
  86     def __init__(self, name):
  87         super().__init__(name)
  88         self.test_name = name
  89     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
  90         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
  91         test_data.append(tc)
  92
  93     def test_rand(self):
  94         insns = ["add", "add.", "subf"]
  95         for i in range(40):
  96             choice = random.choice(insns)
  97             lst = [f"{choice} 3, 1, 2"]
  98             initial_regs = [0] * 32
  99             initial_regs[1] = random.randint(0, (1<<64)-1)
 100             initial_regs[2] = random.randint(0, (1<<64)-1)
 101             self.run_tst_program(Program(lst), initial_regs)
 102
 103     def test_rand_imm(self):
 104         insns = ["addi", "addis", "subfic"]
 105         for i in range(10):
 106             choice = random.choice(insns)
 107             imm = random.randint(-(1<<15), (1<<15)-1)
 108             lst = [f"{choice} 3, 1, {imm}"]
 109             print(lst)
 110             initial_regs = [0] * 32
 111             initial_regs[1] = random.randint(0, (1<<64)-1)
 112             self.run_tst_program(Program(lst), initial_regs)
 113
 114     def test_adde(self):
 115         lst = ["adde. 5, 6, 7"]
 116         for i in range(10):
 117             initial_regs = [0] * 32
 118             initial_regs[6] = random.randint(0, (1<<64)-1)
 119             initial_regs[7] = random.randint(0, (1<<64)-1)
 120             initial_sprs = {}
 121             xer = SelectableInt(0, 64)
 122             xer[XER_bits['CA']] = 1
 123             initial_sprs[special_sprs['XER']] = xer
 124             self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 125
 126     def test_cmp(self):
 127         lst = ["subf. 1, 6, 7",
 128                "cmp cr2, 1, 6, 7"]
 129         initial_regs = [0] * 32
 130         initial_regs[6] = 0x10
 131         initial_regs[7] = 0x05
 132         self.run_tst_program(Program(lst), initial_regs, {})
 133
 134     def test_extsb(self):
 135         insns = ["extsb", "extsh", "extsw"]
 136         for i in range(10):
 137             choice = random.choice(insns)
 138             lst = [f"{choice} 3, 1"]
 139             print(lst)
 140             initial_regs = [0] * 32
 141             initial_regs[1] = random.randint(0, (1<<64)-1)
 142             self.run_tst_program(Program(lst), initial_regs)
 143
 144     def test_cmpeqb(self):
 145         lst = ["cmpeqb cr1, 1, 2"]
 146         for i in range(20):
 147             initial_regs = [0] * 32
 148             initial_regs[1] = i
 149             initial_regs[2] = 0x0001030507090b0f
 150             self.run_tst_program(Program(lst), initial_regs, {})
 151
 152     def test_ilang(self):
 153         pspec = ALUPipeSpec(id_wid=2)
 154         alu = ALUBasePipe(pspec)
 155         vl = rtlil.convert(alu, ports=alu.ports())
 156         with open("alu_pipeline.il", "w") as f:
 157             f.write(vl)
 158
 159
 160 class TestRunner(FHDLTestCase):
 161     def __init__(self, test_data):
 162         super().__init__("run_all")
 163         self.test_data = test_data
 164
 165     def run_all(self):
 166         m = Module()
 167         comb = m.d.comb
 168         instruction = Signal(32)
 169
 170         pdecode = create_pdecode()
 171
 172         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 173
 174         pspec = ALUPipeSpec(id_wid=2)
 175         m.submodules.alu = alu = ALUBasePipe(pspec)
 176
 177         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 178         comb += alu.p.valid_i.eq(1)
 179         comb += alu.n.ready_i.eq(1)
 180         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 181         sim = Simulator(m)
 182
 183         sim.add_clock(1e-6)
 184         def process():
 185             for test in self.test_data:
 186                 print(test.name)
 187                 program = test.program
 188                 self.subTest(test.name)
 189                 simulator = ISA(pdecode2, test.regs, test.sprs, 0)
 190                 gen = program.generate_instructions()
 191                 instructions = list(zip(gen, program.assembly.splitlines()))
 192
 193                 index = simulator.pc.CIA.value//4
 194                 while index < len(instructions):
 195                     ins, code = instructions[index]
 196
 197                     print("0x{:X}".format(ins & 0xffffffff))
 198                     print(code)
 199
 200                     # ask the decoder to decode this binary data (endian'd)
 201                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 202                     yield instruction.eq(ins)          # raw binary instr.
 203                     yield Settle()
 204                     fn_unit = yield pdecode2.e.fn_unit
 205                     self.assertEqual(fn_unit, Function.ALU.value)
 206                     yield from set_alu_inputs(alu, pdecode2, simulator)
 207                     yield from set_extra_alu_inputs(alu, pdecode2, simulator)
 208                     yield
 209                     opname = code.split(' ')[0]
 210                     yield from simulator.call(opname)
 211                     index = simulator.pc.CIA.value//4
 212
 213                     vld = yield alu.n.valid_o
 214                     while not vld:
 215                         yield
 216                         vld = yield alu.n.valid_o
 217                     yield
 218                     alu_out = yield alu.n.data_o.o.data
 219                     out_reg_valid = yield pdecode2.e.write_reg.ok
 220                     if out_reg_valid:
 221                         write_reg_idx = yield pdecode2.e.write_reg.data
 222                         expected = simulator.gpr(write_reg_idx).value
 223                         print(f"expected {expected:x}, actual: {alu_out:x}")
 224                         self.assertEqual(expected, alu_out, code)
 225                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 226                                                             simulator, code)
 227
 228         sim.add_sync_process(process)
 229         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 230                             traces=[]):
 231             sim.run()
 232
 233     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 234         rc = yield dec2.e.rc.data
 235         op = yield dec2.e.insn_type
 236         cridx_ok = yield dec2.e.write_cr.ok
 237         cridx = yield dec2.e.write_cr.data
 238
 239         print ("check extra output", repr(code), cridx_ok, cridx)
 240         if rc:
 241             self.assertEqual(cridx, 0, code)
 242
 243         if cridx_ok:
 244             cr_expected = sim.crl[cridx].get_range().value
 245             cr_actual = yield alu.n.data_o.cr0.data
 246             print ("CR", cridx, cr_expected, cr_actual)
 247             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
 248
 249         cry_out = yield dec2.e.output_carry
 250         if cry_out:
 251             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 252             real_carry = yield alu.n.data_o.xer_ca.data[0] # XXX CO not CO32
 253             self.assertEqual(expected_carry, real_carry, code)
 254             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 255             real_carry32 = yield alu.n.data_o.xer_ca.data[1] # XXX CO32
 256             self.assertEqual(expected_carry32, real_carry32, code)
 257
 258
 259
 260 if __name__ == "__main__":
 261     unittest.main(exit=False)
 262     suite = unittest.TestSuite()
 263     suite.addTest(TestRunner(test_data))
 264
 265     runner = unittest.TextTestRunner()
 266     runner.run(suite)