124752501b21db14d1f9879c09bbaa26a39d357d
2 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
4 # XXX bad practice: use of global variables
5 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
# creates the tests
6 from soc
.fu
.alu
.test
.test_pipe_caller
import test_data
# imports the data
8 from soc
.fu
.compunits
.compunits
import ALUFunctionUnit
9 from soc
.fu
.compunits
.test
.test_compunit
import TestRunner
12 class ALUTestRunner(TestRunner
):
13 def __init__(self
, test_data
):
14 super().__init
__(test_data
, ALUFunctionUnit
, self
,
17 def get_cu_inputs(self
, dec2
, sim
):
18 """naming (res) must conform to ALUFunctionUnit input regspec
23 reg1_ok
= yield dec2
.e
.read_reg1
.ok
25 data1
= yield dec2
.e
.read_reg1
.data
26 res
['ra'] = sim
.gpr(data1
).value
29 reg2_ok
= yield dec2
.e
.read_reg2
.ok
31 data2
= yield dec2
.e
.read_reg2
.data
32 res
['rb'] = sim
.gpr(data2
).value
35 carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
36 carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
37 res
['xer_ca'] = carry |
(carry32
<<1)
40 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
45 def check_cu_outputs(self
, res
, dec2
, sim
, code
):
46 """naming (res) must conform to ALUFunctionUnit output regspec
50 out_reg_valid
= yield dec2
.e
.write_reg
.ok
52 write_reg_idx
= yield dec2
.e
.write_reg
.data
53 expected
= sim
.gpr(write_reg_idx
).value
55 print(f
"expected {expected:x}, actual: {cu_out:x}")
56 self
.assertEqual(expected
, cu_out
, code
)
58 rc
= yield dec2
.e
.rc
.data
59 op
= yield dec2
.e
.insn_type
60 cridx_ok
= yield dec2
.e
.write_cr
.ok
61 cridx
= yield dec2
.e
.write_cr
.data
63 print ("check extra output", repr(code
), cridx_ok
, cridx
)
66 self
.assertEqual(cridx_ok
, 1, code
)
67 self
.assertEqual(cridx
, 0, code
)
71 cr_expected
= sim
.crl
[cridx
].get_range().value
72 cr_actual
= res
['cr_a']
73 print ("CR", cridx
, cr_expected
, cr_actual
)
74 self
.assertEqual(cr_expected
, cr_actual
, "CR%d %s" % (cridx
, code
))
77 cry_out
= yield dec2
.e
.output_carry
79 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
80 xer_ca
= res
['xer_ca']
81 real_carry
= xer_ca
& 0b1 # XXX CO not CO32
82 self
.assertEqual(expected_carry
, real_carry
, code
)
83 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
84 real_carry32
= bool(xer_ca
& 0b10) # XXX CO32
85 self
.assertEqual(expected_carry32
, real_carry32
, code
)
87 # TODO: XER.ov and XER.so
88 oe
= yield dec2
.e
.oe
.data
90 xer_ov
= res
['xer_ov']
91 xer_so
= res
['xer_so']
94 if __name__
== "__main__":
95 unittest
.main(exit
=False)
96 suite
= unittest
.TestSuite()
97 suite
.addTest(ALUTestRunner(test_data
))
99 runner
= unittest
.TextTestRunner()