src/soc/fu/mul/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.mul.pipeline import MulBasePipe
  17 from soc.fu.mul.pipe_data import MulPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to MulFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
  29
  30     print ("alu get_cu_inputs", res)
  31
  32     return res
  33
  34
  35
  36 def set_alu_inputs(alu, dec2, sim):
  37     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  38     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  39     # and place it into data_i.b
  40
  41     inp = yield from get_cu_inputs(dec2, sim)
  42     print ("set alu inputs", inp)
  43     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  44     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  45
  46     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  47
  48
  49 # This test bench is a bit different than is usual. Initially when I
  50 # was writing it, I had all of the tests call a function to create a
  51 # device under test and simulator, initialize the dut, run the
  52 # simulation for ~2 cycles, and assert that the dut output what it
  53 # should have. However, this was really slow, since it needed to
  54 # create and tear down the dut and simulator for every test case.
  55
  56 # Now, instead of doing that, every test case in MulTestCase puts some
  57 # data into the test_data list below, describing the instructions to
  58 # be tested and the initial state. Once all the tests have been run,
  59 # test_data gets passed to TestRunner which then sets up the DUT and
  60 # simulator once, runs all the data through it, and asserts that the
  61 # results match the pseudocode sim at every cycle.
  62
  63 # By doing this, I've reduced the time it takes to run the test suite
  64 # massively. Before, it took around 1 minute on my computer, now it
  65 # takes around 3 seconds
  66
  67
  68 class MulTestCase(FHDLTestCase):
  69     test_data = []
  70
  71     def __init__(self, name):
  72         super().__init__(name)
  73         self.test_name = name
  74
  75     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  76         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  77         self.test_data.append(tc)
  78
  79     def tst_0_mullw(self):
  80         lst = [f"mullw 3, 1, 2"]
  81         initial_regs = [0] * 32
  82         #initial_regs[1] = 0xffffffffffffffff
  83         #initial_regs[2] = 0xffffffffffffffff
  84         initial_regs[1] = 0x2ffffffff
  85         initial_regs[2] = 0x2
  86         self.run_tst_program(Program(lst), initial_regs)
  87
  88     def tst_1_mullwo_(self):
  89         lst = [f"mullwo. 3, 1, 2"]
  90         initial_regs = [0] * 32
  91         initial_regs[1] = 0x3b34b06f
  92         initial_regs[2] = 0xfdeba998
  93         self.run_tst_program(Program(lst), initial_regs)
  94
  95     def tst_2_mullwo(self):
  96         lst = [f"mullwo 3, 1, 2"]
  97         initial_regs = [0] * 32
  98         initial_regs[1] = 0xffffffffffffa988 # -5678
  99         initial_regs[2] = 0xffffffffffffedcc # -1234
 100         self.run_tst_program(Program(lst), initial_regs)
 101
 102     def tst_3_mullw(self):
 103         lst = ["mullw 3, 1, 2",
 104                "mullw 3, 1, 2"]
 105         initial_regs = [0] * 32
 106         initial_regs[1] = 0x6
 107         initial_regs[2] = 0xe
 108         self.run_tst_program(Program(lst), initial_regs)
 109
 110     def test_4_mullw_rand(self):
 111         for i in range(40):
 112             lst = ["mullw 3, 1, 2"]
 113             initial_regs = [0] * 32
 114             initial_regs[1] = random.randint(0, (1<<64)-1)
 115             initial_regs[2] = random.randint(0, (1<<64)-1)
 116             self.run_tst_program(Program(lst), initial_regs)
 117
 118     def test_4_mullw_nonrand(self):
 119         for i in range(40):
 120             lst = ["mullw 3, 1, 2"]
 121             initial_regs = [0] * 32
 122             initial_regs[1] = i+1
 123             initial_regs[2] = i+20
 124             self.run_tst_program(Program(lst), initial_regs)
 125
 126     def tst_rand_mullw(self):
 127         insns = ["mullw", "mullw.", "mullwo", "mullwo."]
 128         for i in range(40):
 129             choice = random.choice(insns)
 130             lst = [f"{choice} 3, 1, 2"]
 131             initial_regs = [0] * 32
 132             initial_regs[1] = random.randint(0, (1<<64)-1)
 133             initial_regs[2] = random.randint(0, (1<<64)-1)
 134             self.run_tst_program(Program(lst), initial_regs)
 135
 136     def test_ilang(self):
 137         pspec = MulPipeSpec(id_wid=2)
 138         alu = MulBasePipe(pspec)
 139         vl = rtlil.convert(alu, ports=alu.ports())
 140         with open("mul_pipeline.il", "w") as f:
 141             f.write(vl)
 142
 143
 144 class TestRunner(FHDLTestCase):
 145     def __init__(self, test_data):
 146         super().__init__("run_all")
 147         self.test_data = test_data
 148
 149     def run_all(self):
 150         m = Module()
 151         comb = m.d.comb
 152         instruction = Signal(32)
 153
 154         pdecode = create_pdecode()
 155
 156         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 157
 158         pspec = MulPipeSpec(id_wid=2)
 159         m.submodules.alu = alu = MulBasePipe(pspec)
 160
 161         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 162         comb += alu.n.ready_i.eq(1)
 163         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 164         sim = Simulator(m)
 165
 166         sim.add_clock(1e-6)
 167         def process():
 168             for test in self.test_data:
 169                 print(test.name)
 170                 program = test.program
 171                 self.subTest(test.name)
 172                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 173                                 test.mem, test.msr)
 174                 gen = program.generate_instructions()
 175                 instructions = list(zip(gen, program.assembly.splitlines()))
 176                 yield Settle()
 177
 178                 index = sim.pc.CIA.value//4
 179                 while index < len(instructions):
 180                     ins, code = instructions[index]
 181
 182                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 183                     print(code)
 184                     if 'XER' in sim.spr:
 185                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 186                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 187                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 188                         print ("before: so/ov/32", so, ov, ov32)
 189
 190                     # ask the decoder to decode this binary data (endian'd)
 191                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 192                     yield instruction.eq(ins)          # raw binary instr.
 193                     yield Settle()
 194                     fn_unit = yield pdecode2.e.do.fn_unit
 195                     self.assertEqual(fn_unit, Function.MUL.value)
 196                     yield from set_alu_inputs(alu, pdecode2, sim)
 197
 198                     # set valid for one cycle, propagate through pipeline...
 199                     yield alu.p.valid_i.eq(1)
 200                     yield
 201                     yield alu.p.valid_i.eq(0)
 202
 203                     opname = code.split(' ')[0]
 204                     yield from sim.call(opname)
 205                     index = sim.pc.CIA.value//4
 206
 207                     # ...wait for valid to pop out the end
 208                     vld = yield alu.n.valid_o
 209                     while not vld:
 210                         yield
 211                         vld = yield alu.n.valid_o
 212                     yield
 213
 214                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 215                     yield Settle()
 216
 217         sim.add_sync_process(process)
 218         with sim.write_vcd("mul_simulator.vcd", "mul_simulator.gtkw",
 219                             traces=[]):
 220             sim.run()
 221
 222     def check_alu_outputs(self, alu, dec2, sim, code):
 223
 224         rc = yield dec2.e.do.rc.data
 225         cridx_ok = yield dec2.e.write_cr.ok
 226         cridx = yield dec2.e.write_cr.data
 227
 228         print ("check extra output", repr(code), cridx_ok, cridx)
 229         if rc:
 230             self.assertEqual(cridx, 0, code)
 231
 232         oe = yield dec2.e.do.oe.oe
 233         oe_ok = yield dec2.e.do.oe.ok
 234         if not oe or not oe_ok:
 235             # if OE not enabled, XER SO and OV must correspondingly be false
 236             so_ok = yield alu.n.data_o.xer_so.ok
 237             ov_ok = yield alu.n.data_o.xer_ov.ok
 238             self.assertEqual(so_ok, False, code)
 239             self.assertEqual(ov_ok, False, code)
 240
 241         sim_o = {}
 242         res = {}
 243
 244         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 245         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 246         yield from ALUHelpers.get_int_o(res, alu, dec2)
 247         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 248
 249         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 250         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 251         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 252         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 253
 254         ALUHelpers.check_int_o(self, res, sim_o, code)
 255         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 256         ALUHelpers.check_xer_so(self, res, sim_o, code)
 257         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 258
 259
 260 if __name__ == "__main__":
 261     unittest.main(exit=False)
 262     suite = unittest.TestSuite()
 263     suite.addTest(TestRunner(MulTestCase.test_data))
 264
 265     runner = unittest.TextTestRunner()
 266     runner.run(suite)