src/soc/fu/shift_rot/rotator.py

   1 # Manual translation and adaptation of rotator.vhdl from microwatt into nmigen
   2 #
   3
   4 from nmigen import (Elaboratable, Signal, Module, Const, Cat,
   5                     unsigned, signed)
   6 from soc.fu.shift_rot.rotl import ROTL
   7
   8 # note BE bit numbering
   9 def right_mask(m, mask_begin):
  10     ret = Signal(64, name="right_mask", reset_less=True)
  11     with m.If(mask_begin <= 64):
  12         m.d.comb += ret.eq((1<<(64-mask_begin)) - 1)
  13     return ret
  14
  15 def left_mask(m, mask_end):
  16     ret = Signal(64, name="left_mask", reset_less=True)
  17     m.d.comb += ret.eq(~((1<<(63-mask_end)) - 1))
  18     return ret
  19
  20
  21 class Rotator(Elaboratable):
  22     """Rotator: covers multiple POWER9 rotate functions
  23
  24         supported modes:
  25
  26         * sl[wd]
  27         * rlw*, rldic, rldicr, rldimi
  28         * rldicl, sr[wd]
  29         * sra[wd][i]
  30
  31         use as follows:
  32
  33         * shift = RB[0:7]
  34         * arith = 1 when is_signed
  35         * right_shift = 1 when insn_type is OP_SHR
  36         * clear_left = 1 when insn_type is OP_RLC or OP_RLCL
  37         * clear_right = 1 when insn_type is OP_RLC or OP_RLCR
  38     """
  39     def __init__(self):
  40         # input
  41         self.me = Signal(5, reset_less=True)        # ME field
  42         self.mb = Signal(5, reset_less=True)        # MB field
  43         self.mb_extra = Signal(1, reset_less=True)  # extra bit of mb in MD-form
  44         self.ra = Signal(64, reset_less=True)       # RA
  45         self.rs = Signal(64, reset_less=True)       # RS
  46         self.shift = Signal(7, reset_less=True)     # RB[0:7]
  47         self.is_32bit = Signal(reset_less=True)
  48         self.right_shift = Signal(reset_less=True)
  49         self.arith = Signal(reset_less=True)
  50         self.clear_left = Signal(reset_less=True)
  51         self.clear_right = Signal(reset_less=True)
  52         # output
  53         self.result_o = Signal(64, reset_less=True)
  54         self.carry_out_o = Signal(reset_less=True)
  55
  56     def elaborate(self, platform):
  57         m = Module()
  58         comb = m.d.comb
  59         ra, rs = self.ra, self.rs
  60
  61         # temporaries
  62         rot_in = Signal(64, reset_less=True)
  63         rot_count = Signal(6, reset_less=True)
  64         rot = Signal(64, reset_less=True)
  65         sh = Signal(7, reset_less=True)
  66         mb = Signal(7, reset_less=True)
  67         me = Signal(7, reset_less=True)
  68         mr = Signal(64, reset_less=True)
  69         ml = Signal(64, reset_less=True)
  70         output_mode = Signal(2, reset_less=True)
  71
  72         # First replicate bottom 32 bits to both halves if 32-bit
  73         comb += rot_in[0:32].eq(rs[0:32])
  74         with m.If(self.is_32bit):
  75             comb += rot_in[32:64].eq(rs[0:32])
  76         with m.Else():
  77             comb += rot_in[32:64].eq(rs[32:64])
  78
  79         shift_signed = Signal(signed(6))
  80         comb += shift_signed.eq(self.shift[0:6])
  81
  82         # Negate shift count for right shifts
  83         with m.If(self.right_shift):
  84             comb += rot_count.eq(-shift_signed)
  85         with m.Else():
  86             comb += rot_count.eq(self.shift[0:6])
  87
  88         # ROTL submodule
  89         m.submodules.rotl = rotl = ROTL(64)
  90         comb += rotl.a.eq(rot_in)
  91         comb += rotl.b.eq(rot_count)
  92         comb += rot.eq(rotl.o)
  93
  94         # Trim shift count to 6 bits for 32-bit shifts
  95         comb += sh.eq(Cat(self.shift[0:6], self.shift[6] & ~self.is_32bit))
  96
  97         # XXX errr... we should already have these, in Fields?  oh well
  98         # Work out mask begin/end indexes (caution, big-endian bit numbering)
  99
 100         # mask-begin (mb)
 101         with m.If(self.clear_left):
 102             comb += mb.eq(self.mb)
 103             with m.If(self.is_32bit):
 104                 comb += mb[5:7].eq(Const(0b01, 2))
 105             with m.Else():
 106                 comb += mb[5:7].eq(Cat(self.mb_extra, Const(0b0, 1)))
 107         with m.Elif(self.right_shift):
 108             # this is basically mb = sh + (is_32bit? 32: 0);
 109             comb += mb.eq(sh)
 110             with m.If(self.is_32bit):
 111                 comb += mb[5:7].eq(Cat(~sh[5], sh[5]))
 112         with m.Else():
 113             comb += mb.eq(Cat(Const(0b0, 5), self.is_32bit, Const(0b0, 1)))
 114
 115         # mask-end (me)
 116         with m.If(self.clear_right & self.is_32bit):
 117             # TODO: track down where this is.  have to use fields.
 118             comb += me.eq(Cat(self.me, Const(0b01, 2)))
 119         with m.Elif(self.clear_right & ~self.clear_left):
 120             # this is me, have to use fields
 121             comb += me.eq(Cat(self.mb, self.mb_extra, Const(0b0, 1)))
 122         with m.Else():
 123             # effectively, 63 - sh
 124             comb += me.eq(Cat(~sh[0:6], sh[6]))
 125
 126         # Calculate left and right masks
 127         comb += mr.eq(right_mask(m, mb))
 128         comb += ml.eq(left_mask(m, me))
 129
 130         # Work out output mode
 131         # 00 for sl[wd]
 132         # 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
 133         # 10 for rldicl, sr[wd]
 134         # 1z for sra[wd][i], z = 1 if rs is negative
 135         with m.If((self.clear_left & ~self.clear_right) | self.right_shift):
 136             comb += output_mode.eq(Cat(self.arith & rot_in[63], Const(1, 1)))
 137         with m.Else():
 138             mbgt = self.clear_right & (mb[0:6] > me[0:6])
 139             comb += output_mode.eq(Cat(mbgt, Const(0, 1)))
 140
 141         # Generate output from rotated input and masks
 142         with m.Switch(output_mode):
 143             with m.Case(0b00):
 144                 comb += self.result_o.eq((rot & (mr & ml)) | (ra & ~(mr & ml)))
 145             with m.Case(0b01):
 146                 comb += self.result_o.eq((rot & (mr | ml)) | (ra & ~(mr | ml)))
 147             with m.Case(0b10):
 148                 comb += self.result_o.eq(rot & mr)
 149             with m.Case(0b11):
 150                 comb += self.result_o.eq(rot | ~mr)
 151                 # Generate carry output for arithmetic shift right of -ve value
 152                 comb += self.carry_out_o.eq(rs & ~ml)
 153
 154         return m
 155