src/soc/litex/florent/libresoc/ls180.py

   1 #
   2 # This file is part of LiteX.
   3 #
   4 # Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
   5 # SPDX-License-Identifier: BSD-2-Clause
   6
   7 """ls180 ASIC platform
   8
   9 conceptually similar to the following:
  10
  11 * https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py
  12 * https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py
  13
  14 """
  15
  16 from migen.fhdl.structure import _Fragment
  17 from litex.build.generic_platform import (GenericPlatform, Pins,
  18                                         Subsignal, IOStandard, Misc,
  19                                         )
  20 import os
  21
  22 # IOs ----------------------------------------------------------------------------------------------
  23
  24 _io = [
  25     ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
  26     ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
  27
  28     ("jtag", 0,
  29         Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
  30         Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
  31         Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
  32         Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
  33     ),
  34
  35     ("serial", 0,
  36         Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
  37         Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
  38     ),
  39
  40     ("serial", 1,
  41         Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
  42         Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
  43     ),
  44
  45     ("spi_master", 0,
  46         Subsignal("clk",  Pins("J1")),
  47         Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  48         Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  49         Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  50         Misc("SLEWRATE=FAST"),
  51         IOStandard("LVCMOS33"),
  52     ),
  53
  54     ("spisdcard", 0,
  55         Subsignal("clk",  Pins("J1")),
  56         Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
  57         Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
  58         Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
  59         Misc("SLEWRATE=FAST"),
  60         IOStandard("LVCMOS33"),
  61     ),
  62
  63     ("sdcard", 0,
  64         Subsignal("clk",  Pins("J1")),
  65         Subsignal("cmd",  Pins("J3"), Misc("PULLMODE=UP")),
  66         Subsignal("data", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
  67         Misc("SLEWRATE=FAST"),
  68         IOStandard("LVCMOS33"),
  69     ),
  70
  71     ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
  72     ("sdram", 0,
  73         Subsignal("a",     Pins(
  74             "M20 M19 L20 L19 K20 K19 K18 J20",
  75             "J19 H20 N19 G20 G19")),
  76         Subsignal("dq",    Pins(
  77             "J16 L18 M18 N18 P18 T18 T17 U20",
  78             "E19 D20 D19 C20 E18 F18 J18 J17")),
  79         Subsignal("we_n",  Pins("T20")),
  80         Subsignal("ras_n", Pins("R20")),
  81         Subsignal("cas_n", Pins("T19")),
  82         Subsignal("cs_n",  Pins("P20")),
  83         Subsignal("cke",   Pins("F20")),
  84         Subsignal("ba",    Pins("P19 N20")),
  85         Subsignal("dm",    Pins("U19 E20")),
  86         IOStandard("LVCMOS33"),
  87         Misc("SLEWRATE=FAST"),
  88     ),
  89
  90     ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")),
  91     ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")),
  92 ]
  93
  94 if False:
  95     pinbank1 = []
  96     pinbank2 = []
  97     for i in range(8):
  98         pinbank1.append("X%d" % i)
  99         pinbank2.append("Y%d" % i)
 100     pins = ' '.join(pinbank1 + pinbank2)
 101
 102     # 16 GPIOs
 103     _io.append( ("gpio", 16, Pins(pins), IOStandard("LVCMOS33")) )
 104
 105 pinsin = []
 106 pinsout = []
 107 for i in range(8):
 108     pinsin.append("X%d" % i)
 109     pinsout.append("Y%d" % i)
 110 pinsin = ' '.join(pinsin)
 111 pinsout = ' '.join(pinsout)
 112
 113 # 8 GPIO in, 8 GPIO out
 114 _io.append( ("gpio_in", 8, Pins(pinsin), IOStandard("LVCMOS33")) )
 115 _io.append( ("gpio_out", 8, Pins(pinsout), IOStandard("LVCMOS33")) )
 116
 117 # 3 External INT wires
 118 _io.append( ("eint", 3, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
 119
 120 # Platform -----------------------------------------------------------------------------------------
 121
 122 class LS180Platform(GenericPlatform):
 123     default_clk_name   = "sys_clk"
 124     default_clk_period = 1e9/50e6
 125
 126     def __init__(self, device="LS180", **kwargs):
 127         assert device in ["LS180"]
 128         GenericPlatform.__init__(self, device, _io, **kwargs)
 129
 130     def build(self, fragment,
 131                     build_dir      = "build",
 132                     build_name     = "top",
 133                     run            = True,
 134                     timingstrict   = True,
 135                     **kwargs):
 136
 137         platform = self
 138
 139         # Create build directory
 140         os.makedirs(build_dir, exist_ok=True)
 141         cwd = os.getcwd()
 142         os.chdir(build_dir)
 143
 144         # Finalize design
 145         if not isinstance(fragment, _Fragment):
 146             fragment = fragment.get_fragment()
 147         platform.finalize(fragment)
 148
 149         # Generate verilog
 150         v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
 151         named_sc, named_pc = platform.resolve_signals(v_output.ns)
 152         v_file = build_name + ".v"
 153         v_output.write(v_file)
 154         platform.add_source(v_file)
 155
 156         os.chdir(cwd)
 157
 158         return v_output.ns
 159
 160     def do_finalize(self, fragment):
 161         super().do_finalize(fragment)
 162         return
 163         self.add_period_constraint(self.lookup_request("clk", loose=True),
 164                                    1e9/50e6)