src/soc/litex/sim.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # This file is Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
   5 # License: BSD
   6
   7 import argparse
   8
   9 from migen import *
  10
  11 from litex.build.generic_platform import Pins, Subsignal
  12 from litex.build.sim import SimPlatform
  13 from litex.build.sim.config import SimConfig
  14
  15 from litex.soc.integration.soc import SoCRegion
  16 from litex.soc.integration.soc_core import SoCCore
  17 from litex.soc.integration.common import get_mem_data
  18
  19 from litedram.modules import MT41K128M16
  20 from litedram.phy.model import SDRAMPHYModel
  21 from litedram.core.controller import ControllerSettings
  22
  23 from litex.tools.litex_sim import get_sdram_phy_settings
  24
  25 from soc.litex.core import LibreSOC
  26
  27 # IOs ------------------------------------------------------------------
  28
  29 _io = [
  30     ("sys_clk", 0, Pins(1)),
  31     ("sys_rst", 0, Pins(1)),
  32     ("serial", 0,
  33         Subsignal("source_valid", Pins(1)),
  34         Subsignal("source_ready", Pins(1)),
  35         Subsignal("source_data",  Pins(8)),
  36
  37         Subsignal("sink_valid", Pins(1)),
  38         Subsignal("sink_ready", Pins(1)),
  39         Subsignal("sink_data",  Pins(8)),
  40     ),
  41 ]
  42
  43 # Platform --------------------------------------------------------------
  44
  45 class Platform(SimPlatform):
  46     def __init__(self):
  47         SimPlatform.__init__(self, "SIM", _io)
  48
  49 # SoCSMP ----------------------------------------------------------------
  50
  51 class SoCSMP(SoCCore):
  52     def __init__(self, cpu_variant, init_memories=False, with_sdcard=False):
  53         platform     = Platform()
  54         sys_clk_freq = int(100e6)
  55
  56         sdram_init = []
  57         if init_memories:
  58             sdram_init = get_mem_data({
  59                 "images/fw_jump.bin": "0x00f00000",
  60                 "images/Image":       "0x00000000",
  61                 "images/dtb"  :       "0x00ef0000",
  62                 "images/rootfs.cpio": "0x01000000",
  63                 }, "little")
  64
  65         # SoCCore --------------------------------------------------------
  66         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
  67             cpu_type                 = "libre-soc",
  68             cpu_variant=cpu_variant,
  69             cpu_cls=LibreSOC,
  70             uart_name                = "sim",
  71             integrated_rom_size      = 0x8000,
  72             integrated_main_ram_size = 0x00000000)
  73         self.platform.name = "sim"
  74         self.add_constant("SIM")
  75
  76         # SDRAM ----------------------------------------------------------
  77         phy_settings = get_sdram_phy_settings(
  78             memtype    = "DDR3",
  79             data_width = 16,
  80             clk_freq   = 100e6)
  81         self.submodules.sdrphy = SDRAMPHYModel(
  82             module    = MT41K128M16(100e6, "1:4"),
  83             settings  = phy_settings,
  84             clk_freq  = 100e6,
  85             init      = sdram_init)
  86         self.add_sdram("sdram",
  87             phy                     = self.sdrphy,
  88             module                  = MT41K128M16(100e6, "1:4"),
  89             origin                  = self.mem_map["main_ram"],
  90             controller_settings     = ControllerSettings(
  91                 cmd_buffer_buffered = False,
  92                 with_auto_precharge = True
  93             )
  94         )
  95         if init_memories:
  96             addr = 0x40f00000
  97             self.add_constant("MEMTEST_BUS_SIZE",  0) # Skip test if memory is
  98             self.add_constant("MEMTEST_ADDR_SIZE", 0) # initialized to avoid
  99             self.add_constant("MEMTEST_DATA_SIZE", 0) # corrumpting the content.
 100             self.add_constant("ROM_BOOT_ADDRESS", addr) # Jump to fw_jump.bin
 101         else:
 102             self.add_constant("MEMTEST_BUS_SIZE",  4096)
 103             self.add_constant("MEMTEST_ADDR_SIZE", 4096)
 104             self.add_constant("MEMTEST_DATA_SIZE", 4096)
 105
 106         # SDCard -----------------------------------------------------
 107         if with_sdcard:
 108             self.add_sdcard("sdcard", use_emulator=True)
 109
 110 # Build --------------------------------------------------------------------------------------------
 111
 112 def main():
 113     parser = argparse.ArgumentParser(
 114                         description="Linux on LiteX-LibreSOC Simulation")
 115     parser.add_argument("--cpu-variant", default="standard",
 116                         help="Select CPU netlist variant")
 117     parser.add_argument("--sdram-init",  action="store_true",
 118                         help="Init SDRAM with Linux images")
 119     parser.add_argument("--with-sdcard", action="store_true",
 120                         help="Enable SDCard support")
 121     parser.add_argument("--trace",       action="store_true",
 122                         help="Enable VCD tracing")
 123     parser.add_argument("--trace-start", default=0,
 124                         help="Cycle to start VCD tracing")
 125     parser.add_argument("--trace-end",   default=-1,
 126                         help="Cycle to end VCD tracing")
 127     parser.add_argument("--opt-level",   default="O3",
 128                         help="Compilation optimization level")
 129     args = parser.parse_args()
 130
 131     sim_config = SimConfig(default_clk="sys_clk")
 132     sim_config.add_module("serial2console", "serial")
 133
 134     for i in range(2):
 135         to_run = (i != 0) # first build, then run
 136         soc = SoCSMP(args.cpu_variant, args.sdram_init and to_run,
 137                      args.with_sdcard)
 138         builder = Builder(soc,
 139             compile_gateware = to_run,
 140             csr_json         = "build/sim/csr.json")
 141         builder.build(sim_config=sim_config,
 142             run         = i!=0,
 143             opt_level   = args.opt_level,
 144             trace       = args.trace,
 145             trace_start = int(args.trace_start),
 146             trace_end   = int(args.trace_end),
 147             trace_fst   = 1)
 148         os.chdir("../")
 149         #if not to_run:
 150         #  os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME
 151         #  os.system("dtc -O dtb -o images/dtb build/sim/dts") # FIXME
 152         #  os.system("cp verilog/*.bin build/sim/gateware/")
 153
 154 if __name__ == "__main__":
 155     main()