src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.decode2execute1 import Data
  25 from soc.experiment.testmem import TestMemory # test only for instructions
  26 from soc.regfile.regfiles import FastRegs
  27 from soc.simple.core import NonProductionCore
  28 from soc.config.test.test_loadstore import TestMemPspec
  29 from soc.config.ifetch import ConfigFetchUnit
  30 from soc.decoder.power_enums import MicrOp
  31 from soc.debug.dmi import CoreDebug, DMIInterface
  32 from soc.config.state import CoreState
  33
  34
  35 class TestIssuer(Elaboratable):
  36     """TestIssuer - reads instructions from TestMemory and issues them
  37
  38     efficiency and speed is not the main goal here: functional correctness is.
  39     """
  40     def __init__(self, pspec):
  41         # main instruction core
  42         self.core = core = NonProductionCore(pspec)
  43
  44         # Test Instruction memory
  45         self.imem = ConfigFetchUnit(pspec).fu
  46         # one-row cache of instruction read
  47         self.iline = Signal(64) # one instruction line
  48         self.iprev_adr = Signal(64) # previous address: if different, do read
  49
  50         # DMI interface
  51         self.dbg = CoreDebug()
  52
  53         # instruction go/monitor
  54         self.pc_o = Signal(64, reset_less=True)
  55         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
  56         self.core_bigendian_i = Signal()
  57         self.busy_o = Signal(reset_less=True)
  58         self.memerr_o = Signal(reset_less=True)
  59
  60         # FAST regfile read /write ports for PC and MSR
  61         self.fast_r_pc = self.core.regs.rf['fast'].r_ports['cia'] # PC rd
  62         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
  63         self.fast_r_msr = self.core.regs.rf['fast'].r_ports['msr'] # MSR rd
  64
  65         # DMI interface access
  66         self.int_r = self.core.regs.rf['int'].r_ports['dmi'] # INT read
  67
  68         # hack method of keeping an eye on whether branch/trap set the PC
  69         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  70         self.fast_nia.wen.name = 'fast_nia_wen'
  71
  72     def elaborate(self, platform):
  73         m = Module()
  74         comb, sync = m.d.comb, m.d.sync
  75
  76         m.submodules.core = core = DomainRenamer("coresync")(self.core)
  77         m.submodules.imem = imem = self.imem
  78         m.submodules.dbg = dbg = self.dbg
  79
  80         # convenience
  81         dmi = dbg.dmi
  82         d_reg = dbg.dbg_gpr
  83
  84         # clock delay power-on reset
  85         cd_por  = ClockDomain(reset_less=True)
  86         cd_sync = ClockDomain()
  87         core_sync = ClockDomain("coresync")
  88         m.domains += cd_por, cd_sync, core_sync
  89
  90         delay = Signal(range(4), reset=1)
  91         with m.If(delay != 0):
  92             m.d.por += delay.eq(delay - 1)
  93         comb += cd_por.clk.eq(ClockSignal())
  94         comb += core_sync.clk.eq(ClockSignal())
  95         # XXX TODO: power-on reset delay (later)
  96         #comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
  97
  98         # busy/halted signals from core
  99         comb += self.busy_o.eq(core.busy_o)
 100         comb += core.bigendian_i.eq(self.core_bigendian_i)
 101
 102         # current state (MSR/PC at the moment
 103         cur_state = CoreState("cur")
 104
 105         # temporary hack: says "go" immediately for both address gen and ST
 106         l0 = core.l0
 107         ldst = core.fus.fus['ldst0']
 108         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 109         m.d.comb += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
 110
 111         # PC and instruction from I-Memory
 112         current_insn = Signal(32) # current fetched instruction (note sync)
 113         pc_changed = Signal() # note write to PC
 114         comb += self.pc_o.eq(cur_state.pc)
 115         ilatch = Signal(32)
 116
 117         # MSR (temp and latched)
 118         msr = Signal(64, reset_less=True)
 119
 120         # next instruction (+4 on current)
 121         nia = Signal(64, reset_less=True)
 122         comb += nia.eq(cur_state.pc + 4)
 123
 124         # connect up debug signals
 125         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 126         comb += core.core_stopped_i.eq(dbg.core_stop_o)
 127         comb += core.core_reset_i.eq(dbg.core_rst_o)
 128         comb += dbg.terminate_i.eq(core.core_terminate_o)
 129         comb += dbg.state.pc.eq(nia)
 130         comb += dbg.state.msr.eq(cur_state.msr)
 131
 132         # temporaries
 133         core_busy_o = core.busy_o         # core is busy
 134         core_ivalid_i = core.ivalid_i     # instruction is valid
 135         core_issue_i = core.issue_i       # instruction is issued
 136         core_be_i = core.bigendian_i      # bigendian mode
 137         core_opcode_i = core.raw_opcode_i # raw opcode
 138
 139         insn_type = core.pdecode2.e.do.insn_type
 140         insn_state = core.pdecode2.state
 141
 142         # actually use a nmigen FSM for the first time (w00t)
 143         # this FSM is perhaps unusual in that it detects conditions
 144         # then "holds" information, combinatorially, for the core
 145         # (as opposed to using sync - which would be on a clock's delay)
 146         # this includes the actual opcode, valid flags and so on.
 147         with m.FSM() as fsm:
 148
 149             # waiting (zzz)
 150             with m.State("IDLE"):
 151                 sync += pc_changed.eq(0)
 152                 with m.If(~dbg.core_stop_o):
 153                     # instruction allowed to go: start by reading the PC
 154                     pc = Signal(64, reset_less=True)
 155                     with m.If(self.pc_i.ok):
 156                         # incoming override (start from pc_i)
 157                         comb += pc.eq(self.pc_i.data)
 158                     with m.Else():
 159                         # otherwise read FastRegs regfile for PC
 160                         comb += self.fast_r_pc.ren.eq(1<<FastRegs.PC)
 161                         comb += pc.eq(self.fast_r_pc.data_o)
 162                     # capture the PC and also drop it into Insn Memory
 163                     # we have joined a pair of combinatorial memory
 164                     # lookups together.  this is Generally Bad.
 165                     comb += self.imem.a_pc_i.eq(pc)
 166                     comb += self.imem.a_valid_i.eq(1)
 167                     comb += self.imem.f_valid_i.eq(1)
 168                     sync += cur_state.pc.eq(pc)
 169                     m.next = "INSN_READ" # move to "wait for bus" phase
 170
 171             # waiting for instruction bus (stays there until not busy)
 172             with m.State("INSN_READ"):
 173                 with m.If(self.imem.f_busy_o): # zzz...
 174                     # busy: stay in wait-read
 175                     comb += self.imem.a_valid_i.eq(1)
 176                     comb += self.imem.f_valid_i.eq(1)
 177                 with m.Else():
 178                     # not busy: instruction fetched
 179                     f_instr_o = self.imem.f_instr_o
 180                     if f_instr_o.width == 32:
 181                         insn = f_instr_o
 182                     else:
 183                         insn = f_instr_o.word_select(cur_state.pc[2], 32)
 184                     comb += current_insn.eq(insn)
 185                     comb += core_ivalid_i.eq(1) # instruction is valid
 186                     comb += core_issue_i.eq(1)  # and issued
 187                     comb += core_opcode_i.eq(current_insn) # actual opcode
 188                     sync += ilatch.eq(current_insn) # latch current insn
 189
 190                     # read MSR, latch it, and put it in decode "state"
 191                     comb += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
 192                     comb += msr.eq(self.fast_r_msr.data_o)
 193                     comb += insn_state.msr.eq(msr)
 194                     sync += cur_state.msr.eq(msr) # latch current MSR
 195
 196                     # also drop PC into decode "state"
 197                     comb += insn_state.pc.eq(cur_state.pc)
 198
 199                     m.next = "INSN_ACTIVE" # move to "wait completion"
 200
 201             # instruction started: must wait till it finishes
 202             with m.State("INSN_ACTIVE"):
 203                 with m.If(insn_type != MicrOp.OP_NOP):
 204                     comb += core_ivalid_i.eq(1) # instruction is valid
 205                 comb += core_opcode_i.eq(ilatch) # actual opcode
 206                 comb += insn_state.eq(cur_state)     # and MSR and PC
 207                 with m.If(self.fast_nia.wen):
 208                     sync += pc_changed.eq(1)
 209                 with m.If(~core_busy_o): # instruction done!
 210                     # ok here we are not reading the branch unit.  TODO
 211                     # this just blithely overwrites whatever pipeline
 212                     # updated the PC
 213                     with m.If(~pc_changed):
 214                         comb += self.fast_w_pc.wen.eq(1<<FastRegs.PC)
 215                         comb += self.fast_w_pc.data_i.eq(nia)
 216                     m.next = "IDLE" # back to idle
 217
 218         # this bit doesn't have to be in the FSM: connect up to read
 219         # regfiles on demand from DMI
 220
 221         with m.If(d_reg.req): # request for regfile access being made
 222             # TODO: error-check this
 223             # XXX should this be combinatorial?  sync better?
 224             comb += self.int_r.ren.eq(1<<d_reg.addr)
 225             comb += d_reg.data.eq(self.int_r.data_o)
 226             comb += d_reg.ack.eq(1)
 227
 228         return m
 229
 230     def __iter__(self):
 231         yield from self.pc_i.ports()
 232         yield self.pc_o
 233         yield self.memerr_o
 234         yield from self.core.ports()
 235         yield from self.imem.ports()
 236         yield self.core_bigendian_i
 237         yield self.busy_o
 238
 239     def ports(self):
 240         return list(self)
 241
 242     def external_ports(self):
 243         return self.pc_i.ports() + [self.pc_o,
 244                                     self.memerr_o,
 245                                     self.core_bigendian_i,
 246                                     ClockSignal(),
 247                                     ResetSignal(),
 248                                     self.busy_o,
 249                                     ] + \
 250                 list(self.dbg.dmi.ports()) + \
 251                 list(self.imem.ibus.fields.values()) + \
 252                 list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
 253
 254     def ports(self):
 255         return list(self)
 256
 257
 258 if __name__ == '__main__':
 259     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 260              'spr': 1,
 261              'mul': 1,
 262              'shiftrot': 1}
 263     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 264                          imem_ifacetype='bare_wb',
 265                          addr_wid=48,
 266                          mask_wid=8,
 267                          reg_wid=64,
 268                          units=units)
 269     dut = TestIssuer(pspec)
 270     vl = main(dut, ports=dut.ports(), name="test_issuer")
 271
 272     if len(sys.argv) == 1:
 273         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 274         with open("test_issuer.il", "w") as f:
 275             f.write(vl)