src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
   7 """
   8 from nmigen import Module, Signal, Cat, ClockSignal
   9 from nmigen.hdl.xfrm import ResetInserter
  10
  11 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  12 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  13 from nmutil.sim_tmp_alternative import Simulator, Settle
  14
  15 from nmutil.formaltest import FHDLTestCase
  16 from nmutil.gtkw import write_gtkw
  17 from nmigen.cli import rtlil
  18 from openpower.decoder.isa.caller import special_sprs, SVP64State
  19 from openpower.decoder.isa.all import ISA
  20 from openpower.endian import bigendian
  21
  22 from openpower.decoder.power_decoder import create_pdecode
  23 from openpower.decoder.power_decoder2 import PowerDecode2
  24 from soc.regfile.regfiles import StateRegs
  25
  26 from soc.simple.issuer import TestIssuerInternal
  27
  28 from soc.config.test.test_loadstore import TestMemPspec
  29 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
  30                                        wait_for_busy_clear,
  31                                        wait_for_busy_hi)
  32 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  33                                                  check_sim_memory)
  34 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  35 from nmutil.util import wrap
  36 from soc.experiment.test.test_mmu_dcache import wb_get
  37 from openpower.test.state import TestState
  38
  39
  40 def setup_i_memory(imem, startaddr, instructions):
  41     mem = imem
  42     print("insn before, init mem", mem.depth, mem.width, mem,
  43           len(instructions))
  44     for i in range(mem.depth):
  45         yield mem._array[i].eq(0)
  46     yield Settle()
  47     startaddr //= 4  # instructions are 32-bit
  48     if mem.width == 32:
  49         mask = ((1 << 32)-1)
  50         for ins in instructions:
  51             if isinstance(ins, tuple):
  52                 insn, code = ins
  53             else:
  54                 insn, code = ins, ''
  55             insn = insn & 0xffffffff
  56             yield mem._array[startaddr].eq(insn)
  57             yield Settle()
  58             if insn != 0:
  59                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  60             startaddr += 1
  61             startaddr = startaddr & mask
  62         return
  63
  64     # 64 bit
  65     mask = ((1 << 64)-1)
  66     for ins in instructions:
  67         if isinstance(ins, tuple):
  68             insn, code = ins
  69         else:
  70             insn, code = ins, ''
  71         insn = insn & 0xffffffff
  72         msbs = (startaddr >> 1) & mask
  73         val = yield mem._array[msbs]
  74         if insn != 0:
  75             print("before set", hex(4*startaddr),
  76                   hex(msbs), hex(val), hex(insn))
  77         lsb = 1 if (startaddr & 1) else 0
  78         val = (val | (insn << (lsb*32)))
  79         val = val & mask
  80         yield mem._array[msbs].eq(val)
  81         yield Settle()
  82         if insn != 0:
  83             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  84             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  85         startaddr += 1
  86         startaddr = startaddr & mask
  87
  88
  89 def set_dmi(dmi, addr, data):
  90     yield dmi.req_i.eq(1)
  91     yield dmi.addr_i.eq(addr)
  92     yield dmi.din.eq(data)
  93     yield dmi.we_i.eq(1)
  94     while True:
  95         ack = yield dmi.ack_o
  96         if ack:
  97             break
  98         yield
  99     yield
 100     yield dmi.req_i.eq(0)
 101     yield dmi.addr_i.eq(0)
 102     yield dmi.din.eq(0)
 103     yield dmi.we_i.eq(0)
 104     yield
 105
 106
 107 def get_dmi(dmi, addr):
 108     yield dmi.req_i.eq(1)
 109     yield dmi.addr_i.eq(addr)
 110     yield dmi.din.eq(0)
 111     yield dmi.we_i.eq(0)
 112     while True:
 113         ack = yield dmi.ack_o
 114         if ack:
 115             break
 116         yield
 117     yield  # wait one
 118     data = yield dmi.dout  # get data after ack valid for 1 cycle
 119     yield dmi.req_i.eq(0)
 120     yield dmi.addr_i.eq(0)
 121     yield dmi.we_i.eq(0)
 122     yield
 123     return data
 124
 125
 126 class TestRunner(FHDLTestCase):
 127     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 128                         svp64=True):
 129         super().__init__("run_all")
 130         self.test_data = tst_data
 131         self.microwatt_mmu = microwatt_mmu
 132         self.rom = rom
 133         self.svp64 = svp64
 134
 135     def run_all(self):
 136         m = Module()
 137         comb = m.d.comb
 138         pc_i = Signal(32)
 139         svstate_i = Signal(64)
 140
 141         if self.microwatt_mmu:
 142             ldst_ifacetype = 'test_mmu_cache_wb'
 143         else:
 144             ldst_ifacetype = 'test_bare_wb'
 145         imem_ifacetype = 'test_bare_wb'
 146
 147         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 148                              imem_ifacetype=imem_ifacetype,
 149                              addr_wid=48,
 150                              mask_wid=8,
 151                              imem_reg_wid=64,
 152                              # wb_data_width=32,
 153                              use_pll=False,
 154                              nocore=False,
 155                              xics=False,
 156                              gpio=False,
 157                              regreduce=True,
 158                              svp64=self.svp64,
 159                              mmu=self.microwatt_mmu,
 160                              reg_wid=64)
 161         #hard_reset = Signal(reset_less=True)
 162         issuer = TestIssuerInternal(pspec)
 163         # use DMI RESET command instead, this does actually work though
 164         #issuer = ResetInserter({'coresync': hard_reset,
 165         #                        'sync': hard_reset})(issuer)
 166         m.submodules.issuer = issuer
 167         imem = issuer.imem._get_memory()
 168         core = issuer.core
 169         dmi = issuer.dbg.dmi
 170         pdecode2 = issuer.pdecode2
 171         l0 = core.l0
 172         regreduce_en = pspec.regreduce_en == True
 173
 174         #simdec = create_pdecode()
 175         simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
 176         m.submodules.simdec2 = simdec2  # pain in the neck
 177
 178         # run core clock at same rate as test clock
 179         intclk = ClockSignal("coresync")
 180         comb += intclk.eq(ClockSignal())
 181
 182         comb += issuer.pc_i.data.eq(pc_i)
 183         comb += issuer.svstate_i.data.eq(svstate_i)
 184
 185         # nmigen Simulation
 186         sim = Simulator(m)
 187         sim.add_clock(1e-6)
 188
 189         def process():
 190
 191             # start in stopped
 192             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 193             yield
 194
 195             # get each test, completely reset the core, and run it
 196
 197             for test in self.test_data:
 198
 199                 # set up bigendian (TODO: don't do this, use MSR)
 200                 yield issuer.core_bigendian_i.eq(bigendian)
 201                 yield Settle()
 202
 203                 yield
 204                 yield
 205                 yield
 206                 yield
 207
 208                 print(test.name)
 209                 program = test.program
 210                 with self.subTest(test.name):
 211                     print("regs", test.regs)
 212                     print("sprs", test.sprs)
 213                     print("cr", test.cr)
 214                     print("mem", test.mem)
 215                     print("msr", test.msr)
 216                     print("assem", program.assembly)
 217                     gen = list(program.generate_instructions())
 218                     insncode = program.assembly.splitlines()
 219                     instructions = list(zip(gen, insncode))
 220
 221                     # Run two tests (TODO, move these to functions)
 222                     # * first the Simulator, collate a batch of results
 223                     # * then the HDL, likewise
 224                     #   (actually, the other way round because running
 225                     #    Simulator somehow modifies the test state!)
 226                     # * finally, compare all the results
 227
 228                     ##########
 229                     # 1. HDL
 230                     ##########
 231
 232                     hdl_states = []
 233
 234                     # establish the TestIssuer context (mem, regs etc)
 235
 236                     pc = 0  # start address
 237                     counter = 0  # test to pause/start
 238
 239                     yield from setup_i_memory(imem, pc, instructions)
 240                     yield from setup_tst_memory(l0, test.mem)
 241                     yield from setup_regs(pdecode2, core, test)
 242
 243                     # set PC and SVSTATE
 244                     yield pc_i.eq(pc)
 245                     yield issuer.pc_i.ok.eq(1)
 246
 247                     initial_svstate = test.svstate
 248                     if isinstance(initial_svstate, int):
 249                         initial_svstate = SVP64State(initial_svstate)
 250                     yield svstate_i.eq(initial_svstate.value)
 251                     yield issuer.svstate_i.ok.eq(1)
 252                     yield
 253
 254                     print("instructions", instructions)
 255
 256                     # run the loop of the instructions on the current test
 257                     index = (yield issuer.cur_state.pc) // 4
 258                     while index < len(instructions):
 259                         ins, code = instructions[index]
 260
 261                         print("hdl instr: 0x{:X}".format(ins & 0xffffffff))
 262                         print(index, code)
 263
 264                         if counter == 0:
 265                             # start the core
 266                             yield
 267                             yield from set_dmi(dmi, DBGCore.CTRL,
 268                                                1<<DBGCtrl.START)
 269                             yield issuer.pc_i.ok.eq(0) # no change PC after this
 270                             yield issuer.svstate_i.ok.eq(0) # ditto
 271                             yield
 272                             yield
 273
 274                         counter = counter + 1
 275
 276                         # wait until executed
 277                         while not (yield issuer.insn_done):
 278                             yield
 279
 280                         yield Settle()
 281
 282                         index = (yield issuer.cur_state.pc) // 4
 283
 284                         terminated = yield issuer.dbg.terminated_o
 285                         print("terminated", terminated)
 286
 287                         if index < len(instructions):
 288                             # Get HDL mem and state
 289                             state = yield from TestState("hdl", core, self,
 290                                                          code)
 291                             hdl_states.append(state)
 292
 293                         if index >= len(instructions):
 294                             print ("index over, send dmi stop")
 295                             # stop at end
 296                             yield from set_dmi(dmi, DBGCore.CTRL,
 297                                                1<<DBGCtrl.STOP)
 298                             yield
 299                             yield
 300
 301                         terminated = yield issuer.dbg.terminated_o
 302                         print("terminated(2)", terminated)
 303                         if terminated:
 304                             break
 305
 306                     ##########
 307                     # 2. Simulator
 308                     ##########
 309
 310                     sim_states = []
 311
 312                     # set up the Simulator (which must track TestIssuer exactly)
 313                     sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 314                               test.msr,
 315                               initial_insns=gen, respect_pc=True,
 316                               disassembly=insncode,
 317                               bigendian=bigendian,
 318                               initial_svstate=test.svstate)
 319
 320                     # run the loop of the instructions on the current test
 321                     index = sim.pc.CIA.value//4
 322                     while index < len(instructions):
 323                         ins, code = instructions[index]
 324
 325                         print("sim instr: 0x{:X}".format(ins & 0xffffffff))
 326                         print(index, code)
 327
 328                         # set up simulated instruction (in simdec2)
 329                         try:
 330                             yield from sim.setup_one()
 331                         except KeyError:  # instruction not in imem: stop
 332                             break
 333                         yield Settle()
 334
 335                         # call simulated operation
 336                         print("sim", code)
 337                         yield from sim.execute_one()
 338                         yield Settle()
 339                         index = sim.pc.CIA.value//4
 340
 341                         # get sim register and memory TestState, add to list
 342                         state = yield from TestState("sim", sim, self, code)
 343                         sim_states.append(state)
 344
 345                     ###############
 346                     # 3. Compare
 347                     ###############
 348
 349                     for simstate, hdlstate in zip(sim_states, hdl_states):
 350                         simstate.compare(hdlstate)     # register check
 351                         simstate.compare_mem(hdlstate) # memory check
 352
 353                     print ("hdl_states")
 354                     for state in hdl_states:
 355                         print (state)
 356
 357                     print ("sim_states")
 358                     for state in sim_states:
 359                         print (state)
 360
 361                     self.assertTrue(len(hdl_states) == len(sim_states),
 362                                     "number of instructions run not the same")
 363
 364                 # stop at end
 365                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 366                 yield
 367                 yield
 368
 369                 # TODO, here is where the static (expected) results
 370                 # can be checked: register check (TODO, memory check)
 371                 # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 372                 # yield from check_regs(self, sim, core, test, code,
 373                 #                       >>>expected_data<<<)
 374
 375                 # get CR
 376                 cr = yield from get_dmi(dmi, DBGCore.CR)
 377                 print("after test %s cr value %x" % (test.name, cr))
 378
 379                 # get XER
 380                 xer = yield from get_dmi(dmi, DBGCore.XER)
 381                 print("after test %s XER value %x" % (test.name, xer))
 382
 383                 # test of dmi reg get
 384                 for int_reg in range(32):
 385                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
 386                     value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
 387
 388                     print("after test %s reg %2d value %x" %
 389                           (test.name, int_reg, value))
 390
 391                 # pull a reset
 392                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 393                 yield
 394
 395         styles = {
 396             'dec': {'base': 'dec'},
 397             'bin': {'base': 'bin'},
 398             'closed': {'closed': True}
 399         }
 400
 401         traces = [
 402             'clk',
 403             ('state machines', 'closed', [
 404                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 405                 'fetch_fsm_state',
 406                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 407                 'pred_insn_i_valid', 'pred_insn_o_ready',
 408                 'fetch_predicate_state',
 409                 'pred_mask_o_valid', 'pred_mask_i_ready',
 410                 'issue_fsm_state',
 411                 'exec_insn_i_valid', 'exec_insn_o_ready',
 412                 'exec_fsm_state',
 413                 'exec_pc_o_valid', 'exec_pc_i_ready',
 414                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 415                 'is_last', 'dec2.no_out_vec']),
 416             {'comment': 'fetch and decode'},
 417             (None, 'dec', [
 418                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
 419                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 420             'raw_insn_i[31:0]',
 421             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 422             ('svp64 decoding', 'closed', [
 423                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 424                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 425                 'dec2.sv_rm_dec.ptype_in',
 426                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 427                 'dstmask[63:0]', 'srcmask[63:0]',
 428                 'dregread[4:0]', 'dinvert',
 429                 'sregread[4:0]', 'sinvert',
 430                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 431                 'core.int.pred__ren']),
 432             ('register augmentation', 'dec', 'closed', [
 433                 {'comment': 'v3.0b registers'},
 434                 'dec2.dec_o.RT[4:0]',
 435                 'dec2.dec_a.RA[4:0]',
 436                 'dec2.dec_b.RB[4:0]',
 437                 ('Rdest', [
 438                     'dec2.o_svdec.reg_in[4:0]',
 439                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 440                     'dec2.o_svdec.reg_out[6:0]']),
 441                 ('Rsrc1', [
 442                     'dec2.in1_svdec.reg_in[4:0]',
 443                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 444                     'dec2.in1_svdec.reg_out[6:0]']),
 445                 ('Rsrc1', [
 446                     'dec2.in2_svdec.reg_in[4:0]',
 447                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 448                     'dec2.in2_svdec.reg_out[6:0]']),
 449                 {'comment': 'SVP64 registers'},
 450                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 451             ]),
 452             {'comment': 'svp64 context'},
 453             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 454             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 455             'core_core_dststep[6:0]',
 456             {'comment': 'issue and execute'},
 457             'core.core_core_insn_type',
 458             (None, 'dec', [
 459                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 460             'issue_i', 'busy_o',
 461             {'comment': 'dmi'},
 462             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 463             {'comment': 'instruction memory'},
 464             'imem.sram.rdport.memory(0)[63:0]',
 465             {'comment': 'registers'},
 466             # match with soc.regfile.regfiles.IntRegs port names
 467             'core.int.rp_src1.memory(0)[63:0]',
 468             'core.int.rp_src1.memory(1)[63:0]',
 469             'core.int.rp_src1.memory(2)[63:0]',
 470             'core.int.rp_src1.memory(3)[63:0]',
 471             'core.int.rp_src1.memory(4)[63:0]',
 472             'core.int.rp_src1.memory(5)[63:0]',
 473             'core.int.rp_src1.memory(6)[63:0]',
 474             'core.int.rp_src1.memory(7)[63:0]',
 475             'core.int.rp_src1.memory(9)[63:0]',
 476             'core.int.rp_src1.memory(10)[63:0]',
 477             'core.int.rp_src1.memory(13)[63:0]'
 478         ]
 479
 480         # PortInterface module path varies depending on MMU option
 481         if self.microwatt_mmu:
 482             pi_module = 'core.ldst0'
 483         else:
 484             pi_module = 'core.fus.ldst0'
 485
 486         traces += [('ld/st port interface', {'submodule': pi_module}, [
 487             'oper_r__insn_type',
 488             'ldst_port0_is_ld_i',
 489             'ldst_port0_is_st_i',
 490             'ldst_port0_busy_o',
 491             'ldst_port0_addr_i[47:0]',
 492             'ldst_port0_addr_i_ok',
 493             'ldst_port0_addr_ok_o',
 494             'ldst_port0_exc_happened',
 495             'ldst_port0_st_data_i[63:0]',
 496             'ldst_port0_st_data_i_ok',
 497             'ldst_port0_ld_data_o[63:0]',
 498             'ldst_port0_ld_data_o_ok',
 499             'exc_o_happened',
 500             'cancel'
 501         ])]
 502
 503         if self.microwatt_mmu:
 504             traces += [
 505                 {'comment': 'microwatt_mmu'},
 506                 'core.fus.mmu0.alu_mmu0.illegal',
 507                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 508                 'core.fus.mmu0.alu_mmu0.mmu.state',
 509                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 510                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 511                 {'comment': 'wishbone_memory'},
 512                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 513                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 514                 'core.fus.mmu0.alu_mmu0.dcache.we',
 515                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 516                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 517             ]
 518
 519         write_gtkw("issuer_simulator.gtkw",
 520                    "issuer_simulator.vcd",
 521                    traces, styles, module='top.issuer')
 522
 523         # add run of instructions
 524         sim.add_sync_process(process)
 525
 526         # optionally, if a wishbone-based ROM is passed in, run that as an
 527         # extra emulated process
 528         if self.rom is not None:
 529             dcache = core.fus.fus["mmu0"].alu.dcache
 530             default_mem = self.rom
 531             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 532
 533         with sim.write_vcd("issuer_simulator.vcd"):
 534             sim.run()