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(parent: d982e1e) | patch
add alternative pc_reset argument to issuer_verilog.py
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 3 Apr 2022 10:30:44 +0000 (11:30 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 3 Apr 2022 10:31:46 +0000 (11:31 +0100)
commit870738bcf71053f9533087ce67a1a7c2742b4b6d
tree209b7fbee4a3e5e915f616433312a105e9d76d7dtree
parentd982e1ef558d7d3d4b26b4108f1e01d59bf0663dcommit | diff
add alternative pc_reset argument to issuer_verilog.py
which propagates right the way down to core.py
next to msr_reset it is now possible to set the pc_reset value.
these actually have to go into the regfile as initial values,
which will be fun for an ASIC
Makefile diff | blob | history
src/soc/simple/core.py diff | blob | history
src/soc/simple/issuer_verilog.py diff | blob | history