comment output stage

diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index 590612220cab31778d6590089e954c16b8bd1cd3..14953ca3c6057cbe33221f5674f6ae01f2a8b0bd 100644 (file)
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -22,14 +22,14 @@ class ALUOutputStage(PipeModBase):
         m = Module()
         comb = m.d.comb
 
+        # op requests inversion of the output
         o = Signal.like(self.i.o)
         with m.If(self.i.ctx.op.invert_out):
             comb += o.eq(~self.i.o)
         with m.Else():
             comb += o.eq(self.i.o)
-        
-
 
+        # create condition register cr0 and sticky-overflow
         is_zero = Signal(reset_less=True)
         is_positive = Signal(reset_less=True)
         is_negative = Signal(reset_less=True)