add microwatt_mmu boolean variable to core and compunits

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index de88bffd90ad2626a8b44972c5216ae6df10b517..4129d36891e641e588abf9918830b02188880894 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -238,7 +238,7 @@ class AllFunctionUnits(Elaboratable):
 
     """
 
 
     """
 

-    def __init__(self, pspec, pilist=None, div_fsm=True,microwatt_mmu = True):
+    def __init__(self, pspec, pilist=None, div_fsm=True,microwatt_mmu = False):

         addrwid = pspec.addr_wid
         units = pspec.units
         if not isinstance(units, dict):
         addrwid = pspec.addr_wid
         units = pspec.units
         if not isinstance(units, dict):

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index babd3b2a921afbed4c73264fe2546ddb97d1400b..04d3604ec9c741a0668de341968fafea93b2f7bc 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -68,20 +68,16 @@ def sort_fuspecs(fuspecs):
 
 
 class NonProductionCore(Elaboratable):
 
 
 class NonProductionCore(Elaboratable):

-    def __init__(self, pspec):
+    def __init__(self, pspec, microwatt_mmu = False):

         self.pspec = pspec
 
         # single LD/ST funnel for memory access
         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
         pi = self.l0.l0.dports[0]
 
         self.pspec = pspec
 
         # single LD/ST funnel for memory access
         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
         pi = self.l0.l0.dports[0]
 

-        if False:
-            # MMU / DCache
-            self.mmu = MMU()
-            self.dcache = DCache()
-

         # function units (only one each)
         # function units (only one each)

-        self.fus = AllFunctionUnits(pspec, pilist=[pi])
+        self.microwatt_mmu = microwatt_mmu
+        self.fus = AllFunctionUnits(pspec, pilist=[pi], microwatt_mmu = self.microwatt_mmu)

 
         # register files (yes plural)
         self.regs = RegFiles()
 
         # register files (yes plural)
         self.regs = RegFiles()