whew finally located opcodes for managing CRs

diff --git a/libreriscv b/libreriscv
index 5551fb3623f86b4d13d3e9913b7a8fa341d67309..c1791bcf40deecca7c60cb7717bdc3fddb9c3061 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 5551fb3623f86b4d13d3e9913b7a8fa341d67309
+Subproject commit c1791bcf40deecca7c60cb7717bdc3fddb9c3061

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 1763bceff514435cfc61ce0e2d9e63ae10596bb2..d07e54cad87f4b36e4c081fa4ffc392f8af68cee 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -135,13 +135,15 @@ class ISACaller:
         # TODO, needed here:
         # 4.4.4 III p971 SPR (same as GPR except for SPRs - best done as a dict
         # FPR (same as GPR except for FP nums)
-        # 4.2.2 p124 FPSCR
-        # 2.3.1 CR (and sub-fields CR0..CR6)
-        # 2.3.2 LR   (SPR #8)
-        # 2.3.3 CTR  (SPR #9)
-        # 2.3.4 TAR  (SPR #815)
-        # 3.2.2 p45 XER  (SPR #0)
-        # 3.2.3 p46 p232 VRSAVE (SPR #256)
+        # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
+        #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
+        # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
+        #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
+        # 2.3.2 LR   (actually SPR #8)
+        # 2.3.3 CTR  (actually SPR #9)
+        # 2.3.4 TAR  (actually SPR #815)
+        # 3.2.2 p45 XER  (actually SPR #0)
+        # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 
         self.namespace = {'GPR': self.gpr,
                           'MEM': self.mem,