--- /dev/null
+# Demo of cxxrtl SR Latch
+
+shows how to compile a yosys "$sr" instance under the new cxxsim backend
+
+compile and run with "make demo"
--- /dev/null
+from nmigen import *
+from nmigen.back import rtlil
+
+
+sr_set = Signal(3)
+sr_clr = Signal(3)
+q = Signal(3)
+
+m = Module()
+m.submodules += Instance("$sr",
+ p_WIDTH=3,
+ p_SET_POLARITY=1,
+ p_CLR_POLARITY=1,
+ i_SET=sr_set,
+ i_CLR=sr_clr,
+ o_Q=q)
+print(rtlil.convert(m, ports=[sr_set, sr_clr, q]))
--- /dev/null
+#include <stdio.h>
+
+#include "sr.cc"
+
+cxxrtl_design::p_top top;
+
+void step() {
+ top.step();
+ fprintf(stderr, "SET %d CLR %d Q %d\n",
+ top.p_sr__set.data[0], top.p_sr__clr.data[0], top.p_q.data[0]);
+}
+
+int main() {
+ step();
+
+ top.p_sr__set = value<3>{3u};
+ step(); // set bits 0 & 1
+
+ top.p_sr__set = value<3>{0u};
+ top.p_sr__clr = value<3>{1u};
+ step(); // clear bit 0
+
+ top.p_sr__clr = value<3>{0u};
+ step(); // retain latched value
+
+ top.p_sr__set = value<3>{2u};
+ top.p_sr__clr = value<3>{2u};
+ step(); // clear bit 1, since CLR has priority over SET
+
+ return 0;
+}