add indicator to PowerDecoder2 when no outputs are Vectorised

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 8f81acf0b775fba56981da29c6113385bb6ba286..e2e4e8af36120b74f8f7b60fd8a5abb31e1558e6 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -1003,6 +1003,7 @@ class PowerDecode2(PowerDecodeSubset):
         self.in3_isvec = Signal(1, name="reg_c_isvec")
         self.o_isvec = Signal(1, name="reg_o_isvec")
         self.o2_isvec = Signal(1, name="reg_o2_isvec")
+        self.no_out_vec = Signal(1, name="no_out_vec") # no outputs are vectors
 
     def get_col_subset(self, opkls):
         subset = super().get_col_subset(opkls)
@@ -1134,11 +1135,14 @@ class PowerDecode2(PowerDecodeSubset):
         # "update mode" rather than specified cleanly as its own CSV column
         #comb += o2_svdec.idx.eq(op.sv_out)    # SVP64 output (implicit)
 
+        # output reg-is-vectorised (and when no output is vectorised)
         comb += self.in1_isvec.eq(in1_svdec.isvec)
         comb += self.in2_isvec.eq(in2_svdec.isvec)
         comb += self.in3_isvec.eq(in3_svdec.isvec)
         comb += self.o_isvec.eq(o_svdec.isvec)
         comb += self.o2_isvec.eq(o2_svdec.isvec)
+        # TODO: include SPRs and CRs here!  must be True when *all* are scalar
+        comb += self.no_out_vec.eq((~o2_svdec.isvec) & (~o_svdec.isvec))
 
         # SPRs out
         comb += e.read_spr1.eq(dec_a.spr_out)