Add comments about the purpose of each alu stage

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index 6d5e1e46c3ec47a40762331f3bff3b6b9236efc3..77da32f51b888e45fef716b50ad391a91e3bdf60 100644 (file)
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -1,3 +1,7 @@
+# This stage is intended to adjust the input data before sending it to
+# the acutal ALU. Things like handling inverting the input, carry_in
+# generation for subtraction, and handling of immediates should happen
+# here
 from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 615a78452279b7ca32b9cfe07a8d4b7493932d8c..e801c9660a927d6fd8fd7432d578d5f372722fc5 100644 (file)
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -1,3 +1,8 @@
+# This stage is intended to do most of the work of executing the ALU
+# instructions. This would be like the additions, logical operations,
+# and shifting, as well as carry and overflow generation. This module
+# however should not gate the carry or overflow, that's up to the
+# output stage
 from nmigen import (Module, Signal)
 from nmutil.pipemodbase import PipeModBase
 from soc.alu.pipe_data import ALUInputData, ALUOutputData

diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index cb63b0e48f4cb0bfa6c53cf263e0b7330b2aebea..1a8a82b620149ce83aceabe8a0cf6262e7ab58b0 100644 (file)
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -1,3 +1,6 @@
+# This stage is intended to handle the gating of carry and overflow
+# out, summary overflow generation, and updating the condition
+# register
 from nmigen import (Module, Signal, Cat)
 from nmutil.pipemodbase import PipeModBase
 from soc.alu.pipe_data import ALUInputData, ALUOutputData