Replace all hardcoded shifts into RM by usage of SVP64RMFields

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index d5399cb9218405e95eae4e282be35e3872f5c6d4..c78219d8744fc8e1a3275ee23d77d4bb71529f17 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -250,6 +250,16 @@ class SVP64RMFields:
         self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
         self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
         self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
+        self.extra2 = list(range(4))
+        self.extra2[0] = FieldSelectableInt(self.spr, tuple(range(10,12)))
+        self.extra2[1] = FieldSelectableInt(self.spr, tuple(range(12,14)))
+        self.extra2[2] = FieldSelectableInt(self.spr, tuple(range(14,16)))
+        self.extra2[3] = FieldSelectableInt(self.spr, tuple(range(16,18)))
+        self.smask = FieldSelectableInt(self.spr, tuple(range(16,19)))
+        self.extra3 = list(range(3))
+        self.extra3[0] = FieldSelectableInt(self.spr, tuple(range(10,13)))
+        self.extra3[1] = FieldSelectableInt(self.spr, tuple(range(13,16)))
+        self.extra3[2] = FieldSelectableInt(self.spr, tuple(range(16,19)))
         self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
 
 

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index e36b10a567c21606627ec44adabd85190efa7976..726bdacbcd342bd156cedac0d177b4c32c2912fc 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -18,7 +18,8 @@ import os, sys
 from collections import OrderedDict
 
 from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
-                                    SV64P_PID_SIZE, SV64P_RM_SIZE)
+                                    SV64P_PID_SIZE, SV64P_RM_SIZE,
+                                    SVP64RMFields)
 from soc.decoder.pseudo.pagereader import ISA
 from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
 from soc.decoder.selectable_int import SelectableInt
@@ -332,14 +333,15 @@ class SVP64Asm:
             print ("extras", extras)
 
             # rright.  now we have all the info. start creating SVP64 RM
-            svp64_rm = 0b0
+            svp64_rm = SVP64RMFields()
 
             # begin with EXTRA fields
             for idx, sv_extra in extras.items():
                 if idx is None: continue
-                # start at bit 10, work up 2/3 times EXTRA idx
-                offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
-                svp64_rm |= sv_extra << (24-offs-(10+idx*offs))
+                if etype == 'EXTRA2':
+                    svp64_rm.extra2[idx].eq(SelectableInt(sv_extra, 2))
+                else:
+                    svp64_rm.extra3[idx].eq(SelectableInt(sv_extra, 3))
 
             # parts of svp64_rm
             mmode = 0  # bit 0
@@ -506,24 +508,31 @@ class SVP64Asm:
             # whewww.... modes all done :)
             # now put into svp64_rm
             mode |= sv_mode
-            svp64_rm |= (mode << 23-23)       # mode: bits 19-23
+            # mode: bits 19-23
+            svp64_rm.mode.eq(SelectableInt(mode, 5))
 
             # put in predicate masks into svp64_rm
             if ptype == '2P':
-                svp64_rm |= (smask << 23-18)  # source pred: bits 16-18
-            svp64_rm |= (mmode << 23-0)       # mask mode: bit 0
-            svp64_rm |= (pmask << 23-3)       # 1-pred: bits 1-3
+                # source pred: bits 16-18
+                svp64_rm.smask.eq(SelectableInt(smask, 3))
+            # mask mode: bit 0
+            svp64_rm.mmode.eq(SelectableInt(mmode, 1))
+            # 1-pred: bits 1-3
+            svp64_rm.mask.eq(SelectableInt(pmask, 3))
 
-            # and subvl
-            svp64_rm += (subvl << 23-9)       # subvl: bits 8-9
+            # and subvl: bits 8-9
+            svp64_rm.subvl.eq(SelectableInt(subvl, 2))
 
             # put in elwidths
-            svp64_rm += (srcwid << 23-7)      # srcwid: bits 6-7
-            svp64_rm += (destwid << 23-5)     # destwid: bits 4-5
+            # srcwid: bits 6-7
+            svp64_rm.ewsrc.eq(SelectableInt(srcwid, 2))
+            # destwid: bits 4-5
+            svp64_rm.elwidth.eq(SelectableInt(destwid, 2))
 
             # nice debug printout. (and now for something completely different)
             # https://youtu.be/u0WOIwlXE9g?t=146
-            print ("svp64_rm", hex(svp64_rm), bin(svp64_rm))
+            svp64_rm_value = svp64_rm.spr.value
+            print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
             print ("    mmode  0    :", bin(mmode))
             print ("    pmask  1-3  :", bin(pmask))
             print ("    dstwid 4-5  :", bin(destwid))
@@ -545,7 +554,7 @@ class SVP64Asm:
             svp64_prefix = SVP64PrefixFields()
             svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
             svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
-            svp64_prefix.rm.eq(SelectableInt(svp64_rm, SV64P_RM_SIZE))
+            svp64_prefix.rm.eq(svp64_rm.spr)
 
             # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
             rc = '.' if rc_mode else ''