update submodule

diff --git a/libreriscv b/libreriscv
index c932acee1edf6c376a3225f937d243c8a2bf712b..210b57c1f0ebe644c132147f67e543332fc20eeb 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit c932acee1edf6c376a3225f937d243c8a2bf712b
+Subproject commit 210b57c1f0ebe644c132147f67e543332fc20eeb

diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 40d10e8c8962047ee4d46cd6c9430102f7a4cfa9..113b37ebf762eeda39e53d73d9ad2a6e5f433086 100644 (file)
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -72,8 +72,9 @@ class PyISAWriter(ISA):
 
 if __name__ == '__main__':
     isa = PyISAWriter()
-    isa.write_pysource('branch')
+    isa.write_pysource('fixedtrap')
     exit(0)
+    isa.write_pysource('branch')
     isa.write_pysource('fixedlogical')
     isa.write_pysource('fixedstore')
     isa.write_pysource('fixedload')